From c003bd2581866aea2b6257f3ab75063ee4fa4f83 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sat, 15 Apr 2023 07:12:24 -0400 Subject: [PATCH] More comments in RAM controller --- cpld/RAM.v | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/cpld/RAM.v b/cpld/RAM.v index 1fb36a1..2afa2c3 100644 --- a/cpld/RAM.v +++ b/cpld/RAM.v @@ -61,10 +61,14 @@ module RAM( assign RA[01] = !RASEL ? A[10] : A[02]; assign RA[00] = !RASEL ? A[09] : A[01]; - wire RS0toRef = (RefReq && BACT && !BACTr && !RAMCS0X) || - (RefUrg && !RASEN) || + wire RS0toRef = // Refresh during first clock of non-RAM access + (RefReq && BACT && !BACTr && !RAMCS0X) || + // Urgent refresh while bus inactive + (RefUrg && !BACT) || + // Urgent refresh during non-RAM access (RefUrg && BACT && !RAMCS0X) || - (RefUrg && !BACT); + // Urgent refresh if RAM is disabled + (RefUrg && !RASEN); always @(posedge CLK) begin case (RS[2:0])