diff --git a/cpld/CS.v b/cpld/CS.v
index 0010e22..827ecf9 100644
--- a/cpld/CS.v
+++ b/cpld/CS.v
@@ -19,7 +19,7 @@ module CS(
 
 	/* Select signals - FSB domain */
 	assign RAMCS = 0;//(A[23:22]==2'b00) && !Overlay; // 000000-3FFFFF when overlay disabled
-	wire VidRAMCSWR64k = RAMCS && (A[21:20]==2'h3) && (A[19:16]==4'hF) && ~nWE; // 3F0000-3FFFFF / 7F0000-7FFFFF
+	wire VidRAMCSWR64k = RAMCS && !nWE && (A[21:20]==2'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF / 7F0000-7FFFFF
 	wire VidRAMCSWR = VidRAMCSWR64k && (
 		(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
 		(A[15:12]==4'h3) || // 4096 bytes video
diff --git a/cpld/RAM.v b/cpld/RAM.v
index aa0f638..6c250b8 100644
--- a/cpld/RAM.v
+++ b/cpld/RAM.v
@@ -57,8 +57,7 @@ module RAM(
 			else if (!BACT) RAMEN <= 1;
 		end else if (RS==7) begin
 			if (RefFromRS7) RAMEN <= 0;
-			else if (BACT) RAMEN <= 0;
-			else if (!BACT) RAMEN <= 1;
+			else RAMEN <= 1;
 		end
 	end