From cf1b0ec03b93a2bba96dbf5642a753320f103fa3 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sun, 9 Apr 2023 23:26:05 -0400 Subject: [PATCH] Revert "Revert "Share IOPWReady with ALE1 in IOBS"" This reverts commit 388e381dffbac52b96e6708a5b6d923056fda0cb. --- cpld/IOBS.v | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/cpld/IOBS.v b/cpld/IOBS.v index 2d3bb8a..d1240bc 100644 --- a/cpld/IOBS.v +++ b/cpld/IOBS.v @@ -6,7 +6,7 @@ module IOBS( /* Select signals */ input IOCS, input IOPWCS, input ROMCS, /* FSB cycle termination outputs */ - output reg IONPReady, output reg IOPWReady, output reg nBERR_FSB, + output reg IONPReady, output IOPWReady, output reg nBERR_FSB, /* Read data OE control */ output nDinOE, /* IOB master controller interface */ @@ -42,11 +42,8 @@ module IOBS( reg Sent = 0; /* FIFO secondary level control */ - reg Load1; - reg Clear1; - reg IORW1; - reg IOL1; - reg IOU1; + reg Load1; reg Clear1; + reg IORW1; reg IOL1; reg IOU1; always @(posedge CLK) begin // ALE and R/W load control // If write currently posting (TS!=0), // I/O selected, and FIFO secondary level empty @@ -128,19 +125,13 @@ module IOBS( else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1; end - /* Nonposted ready */ - always @(posedge CLK) begin + /* Nonposted and posted ready */ + assign IOPWReady = !ALE1; // Posted write reaedy + always @(posedge CLK) begin // Nonposted read/write ready if (!BACT) IONPReady <= 0; else if (Sent && !IOPWCS && IODONE) IONPReady <= 1; end - /* Posted ready */ - always @(posedge CLK) begin - if (Clear1) IOPWReady <= 1; - else if (Load1) IOPWReady <= 0; - else IOPWReady <= !ALE1; - end - /* BERR control */ always @(posedge CLK) begin if (!BACT) nBERR_FSB <= 1;