diff --git a/cpld/IOBM.v b/cpld/IOBM.v
index 8435738..513dea3 100644
--- a/cpld/IOBM.v
+++ b/cpld/IOBM.v
@@ -7,7 +7,7 @@ module IOBM(
 	input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
 	/* IO bus slave port interface */
 	input IOREQ, input IORW, input IOLDS, input IOUDS,
-	output reg IOACT, output reg IODONE, output reg IOBERR);
+	output reg IOACT, output IODONE);
 
 	/* C8M clock registration */
 	reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
@@ -36,21 +36,26 @@ module IOBM(
 		else if (ES==0) nVMA <= 1;
 	end
 	
-	/* DTACK and BERR synchronization */
-	always @(negedge C8M, posedge nAS) begin
-		if (nAS) begin
-			IODONE <= 0;
-			IOBERR <= 0;
-		end else begin
-			IODONE <= (!nDTACK || ETACK || !nRES);
-			IOBERR <= !nBERR;
-		end
-	end
-
 	/* I/O bus state */
 	reg [2:0] IOS = 0;
 	reg IOS0;
 
+	/* Cycle termination signal enable */
+	reg TermEN;
+	always @(posedge C16M) begin
+		TermEN <= IOS==2 || IOS==3 || IOS==4 || IOS==5;
+	end
+
+	/* DTACK/"ETACK"/BERR/reset falling edge synchronization */
+	reg IODONEr;
+	always @(negedge C8M, posedge nAS) begin
+		if (nAS) IODONEr <= 0;
+		else IODONEr <= TermEN && (!nDTACK || ETACK || !nBERR || !nRES);
+	end
+
+	/* DTACK/"ETACK"/BERR/reset output */
+	assign IODONE = IODONEr && TermEN;
+
 	/* I/O bus control */
 	always @(posedge C16M) case (IOS[2:0])
 		3'h0: begin
@@ -79,7 +84,7 @@ module IOBM(
 			IOACT <= 1;
 			ALE0 <= 1;
 		end 3'h5: begin
-			if (!C8Mr && (IODONE || IOBERR)) begin
+			if (!C8Mr && IODONEr) begin
 				IOS <= 6;
 				IOACT <= 0;
 			end else begin
diff --git a/cpld/IOBS.v b/cpld/IOBS.v
index a689763..01910cc 100644
--- a/cpld/IOBS.v
+++ b/cpld/IOBS.v
@@ -11,7 +11,7 @@ module IOBS(
 	output nDinOE,
 	/* IOB master controller interface */
 	output reg IOREQ, output reg IORW,
-	input IOACT, input IODONEin, input IOBERR,
+	input IOACT, input IODONEin, input nBERR_IOB,
 	/* FIFO primary level control */
 	output reg ALE0, output reg IOL0, output reg IOU0,
 	/* FIFO secondary level control */
@@ -139,6 +139,6 @@ module IOBS(
 	/* BERR control */
 	always @(posedge CLK) begin
 		if (!BACT) nBERR_FSB <= 1;
-		else if (Sent && IOBERR) nBERR_FSB <= 0;
+		else if (Sent && IODONE && nBERR_IOB) nBERR_FSB <= 0;
 	end
 endmodule
diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v
index 98ca64f..349352f 100644
--- a/cpld/WarpSE.v
+++ b/cpld/WarpSE.v
@@ -132,7 +132,7 @@ module WarpSE(
 	wire ALE0S, ALE0M, ALE1;
 	assign nADoutLE0 = ~(ALE0S || ALE0M);
 	assign nADoutLE1 = ~ALE1;
-	wire IOACT, IODONE, IOBERR;
+	wire IOACT, IODONE;
 	IOBS iobs(
 		/* MC68HC000 interface */
 		.CLK(FCLK),
@@ -157,7 +157,7 @@ module WarpSE(
 		.IORW(IORW),
 		.IOACT(IOACT),
 		.IODONEin(IODONE),
-		.IOBERR(IOBERR),
+		.nBERR_IOB(!nBERR_IOB),
 		/* FIFO primary level control */
 		.ALE0(ALE0S),
 		.IOL0(IOL0),
@@ -198,8 +198,7 @@ module WarpSE(
 		.IOLDS(IOL0),
 		.IOUDS(IOU0),
 		.IOACT(IOACT),
-		.IODONE(IODONE),
-		.IOBERR(IOBERR));
+		.IODONE(IODONE));
 
 	wire SndQoSReady;
 	CNT cnt(