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C8M-based POR supports higher fast clock frequencies

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This commit is contained in:
Zane Kaminski 2024-11-04 19:19:31 -05:00
parent a3da23b94a
commit d1f58eb0cc
1 changed files with 3 additions and 3 deletions
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6
cpld/CNT.v
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@ -39,7 +39,7 @@ module CNT(
wire EFall = Er[1] && !Er[0];
/* C8M clock synchronization */
reg [3:0] C8Mr; always @(posedge CLK) C8Mr[3:0] <= { C8Mr[2:0], C8M };
reg [4:0] C8Mr; always @(posedge CLK) C8Mr[4:0] <= { C8Mr[3:0], C8M };
wire C8MFall = C8Mr[1] && !C8Mr[0]; // C8M falling edge detect
/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
@ -128,8 +128,8 @@ module CNT(
/* C8M duty cycle check and power-on reset */
always @(posedge CLK) begin
if (C8Mr[3:0]==4'b0000 || C8Mr[3:0]==4'b1111) nPOR <= 0;
else if (C8Mr[1:0]==2'b01) nPOR <= 1;
if (C8Mr[4:0]==5'b00000 || C8Mr[4:0]==5'b11111) nPOR <= 0;
else if (C8Mr[2:0]==3'b011) nPOR <= 1;
end
/* Startup sequence state control */