diff --git a/cpld/CNT.v b/cpld/CNT.v
index ef32620..4e9b30c 100644
--- a/cpld/CNT.v
+++ b/cpld/CNT.v
@@ -11,11 +11,23 @@ module CNT(
 	input nAS,
 	input ASrf,
 	input BACT,
-	input QoSCS,
-	input SndQoSCS,
+	input IACKCS,
+	input VIACS,
+	input IWMCS,
+	input SCCCS,
+	input SCSICS,
+	input SndCSWR,
+	/* QoS settings inputs */
+	input SlowIACK,
+	input SlowVIA,
+	input SlowIWM,
+	input SlowSCC,
+	input SlowSCSI,
+	input SlowSnd,
+	input SlowClockGate,
+	input [3:0] SlowTimeout,
 	/* QoS outputs */
 	output reg QoSEN,
-	output SndQoSReady,
 	output reg MCKE);
 	
 	/* E clock synchronization */
@@ -57,9 +69,16 @@ module CNT(
 	always @(posedge CLK) TimerTick <= EFall && TimerTC;
 
 	/* QoS select latches */
-	reg QoSCSr, SndQoSCSr;
-	always @(posedge CLK) QoSCSr <= (BACT && QoSCS) || !nRESin;
-	always @(posedge CLK) SndQoSCSr <= BACT && SndQoSCS;
+	reg QoSCSr;
+	always @(posedge CLK) begin
+		QoSCSr <= !nRESin ||
+			(!nAS && SlowIACK  && IACKCS) ||
+			(!nAS && SlowVIA   && VIACS) ||
+			(!nAS && SlowIWM   && IWMCS) ||
+			(!nAS && SlowSCC   && SCCCS) ||
+			(!nAS && SlowSCSI  && SCSICS) ||
+			(!nAS && SlowSnd   && SndCSWR);
+	end
 
 	/* QoS timer
 	 * In the absence of a QoS trigger, QS==0.
@@ -68,19 +87,18 @@ module CNT(
 	 * QoS enable period is 196.588 us - 210.630 us */
 	reg [3:0] QS;
 	always @(posedge CLK) begin
-		if (SndQoSCSr || QoSCSr) QS <= 15;
+		if (QoSCSr) QS <= 15;
 		else if (QS==0) QS <= 0;
 		else if (TimerTick) QS <= QS-1;
 	end
 
 	/* QoS enable control */
-	always @(posedge CLK) if (!BACT) QoSEN <= QS!=0;
-	assign SndQoSReady = 1;
+	always @(posedge CLK) if (!BACT) QoSEN <= QS!=0 || SlowTimeout==0;
 	
 	/* MC68k clock gating during QoS */
 	always @(negedge CLK, negedge nAS) begin
 		if (!nAS) MCKE <= 1;
-		else MCKE <= ASrf || !QoSEN || C8MFall;
+		else MCKE <= ASrf || !QoSEN || C8MFall || !SlowClockGate;
 	end
 	
 	/* Long timer counts from 0 to 4095.
diff --git a/cpld/CS.v b/cpld/CS.v
index 863365e..774dc54 100644
--- a/cpld/CS.v
+++ b/cpld/CS.v
@@ -9,7 +9,9 @@ module CS(
 	output IOCS, output IORealCS, output IOPWCS, output IACS,
 	output ROMCS, output ROMCS4X,
 	output RAMCS, output RAMCS0X,
-	output QoSCS, output SndQoSCS);
+	output IACKCS, output VIACS, output IWMCS, 
+	output SCCCS, output SCSICS, output SndCSWR,
+	output SetCSWR);
 
 	/* Overlay control */
 	reg Overlay;
@@ -19,11 +21,11 @@ module CS(
 	end
 
 	/* I/O select signals */
-	wire IACKCS = A[23:20]==4'hF;
-	wire VIACS = A[23:20]==4'hE;
-	wire IWMCS = A[23:20]==4'hD;
-	wire SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
-	wire SCSICS = A[23:20]==4'h5;
+	assign IACKCS = A[23:20]==4'hF;
+	assign VIACS = A[23:20]==4'hE;
+	assign IWMCS = A[23:20]==4'hD;
+	assign SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
+	assign SCSICS = A[23:20]==4'h5;
 
 	/* ROM select signals */
 	assign ROMCS4X = A[23:20]==4'h4;
@@ -46,11 +48,11 @@ module CS(
 		//A[15:12]==4'hD || // 4096 bytes video
 		//A[15:12]==4'hE || // 4096 bytes video
 		//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
-	wire SndRAMCSWR = VidRAMCSWR64k && (
+	assign SndCSWR = VidRAMCSWR64k && (
 		((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
 		((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
-	assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS;
-	assign SndQoSCS = SndRAMCSWR;
+
+	assign SetCSWR = A[23:20]==4'hF && !A[19];
 
 	/* Select signals - IOB domain */
 	assign IACS = A[23:20]==4'hF; // IACK
diff --git a/cpld/FSB.v b/cpld/FSB.v
index fd24052..dd78814 100644
--- a/cpld/FSB.v
+++ b/cpld/FSB.v
@@ -7,9 +7,9 @@ module FSB(
 	input ROMCS,
 	input RAMCS, input RAMReady,
 	input IOPWCS, input IOPWReady, input IONPReady,
-	input QoSEN, input SndQoSReady,
+	input QoSEN,
 	/* Interrupt acknowledge select */
-	input IACS);
+	input IACKCS);
 
 	/* AS cycle detection */
 	always @(negedge FCLK) begin ASrf <= !nAS; end
@@ -19,15 +19,14 @@ module FSB(
 	/* DTACK/VPA control */
 	wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) ||
                  (RAMCS && !QoSEN && RAMReady &&  IOPWCS && IOPWReady) ||
-                 (ROMCS && !QoSEN) ||
-                 (IONPReady && SndQoSReady);
+                 (ROMCS && !QoSEN) || (IONPReady);
 	always @(posedge FCLK, posedge nAS) begin
 		if (nAS) nDTACK <= 1;
-		else nDTACK <= !(Ready && !IACS);
+		else nDTACK <= !(Ready && !IACKCS);
 	end
 	always @(posedge FCLK, posedge nAS) begin
 		if (nAS) nVPA <= 1;
-		else nVPA <= !(Ready && IACS);
+		else nVPA <= !(Ready && IACKCS);
 	end
 	
 endmodule
diff --git a/cpld/SET.v b/cpld/SET.v
new file mode 100644
index 0000000..9a1203b
--- /dev/null
+++ b/cpld/SET.v
@@ -0,0 +1,30 @@
+module SET(
+	input CLK,
+	input BACT,
+	input [11:1] A,
+	input SetCSWR,
+	output reg SlowIACK,
+	output reg SlowVIA,
+	output reg SlowIWM,
+	output reg SlowSCC,
+	output reg SlowSCSI,
+	output reg SlowSnd,
+	output reg SlowClockGate,
+	output reg [3:0] SlowTimeout);
+	
+	reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
+
+	always @(posedge CLK) begin
+		if (SetWRr) begin
+			SlowTimeout[3:0] <= A[11:8];
+			SlowIACK <= A[7];
+			SlowVIA  <= A[6];
+			SlowIWM  <= A[5];
+			SlowSCC  <= A[4];
+			SlowSCSI <= A[3];
+			SlowSnd  <= A[2];
+			SlowClockGate <= A[1];
+		end
+	end
+
+endmodule
diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v
index fa274d1..2bccc56 100644
--- a/cpld/WarpSE.v
+++ b/cpld/WarpSE.v
@@ -63,10 +63,12 @@ module WarpSE(
 	wire RefReq, RefUrg;
 	
 	/* FSB chip select signals */
-	wire IOCS, IORealCS, IOPWCS, IACS;
+	wire IOCS, IORealCS, IOPWCS;
 	wire ROMCS, ROMCS4X;
 	wire RAMCS, RAMCS0X;
-	wire QoSCS, SndQoSCS, QoSEN;
+	wire QoSEN;
+	wire IACKCS, VIACS, IWMCS, SCCCS, SCSICS, SndCSWR;
+	wire SetCSWR;
 	CS cs(
 		/* MC68HC000 interface */
 		.A(A_FSB[23:08]),
@@ -81,13 +83,19 @@ module WarpSE(
 		.IOCS(IOCS),
 		.IORealCS(IORealCS),
 		.IOPWCS(IOPWCS),
-		.IACS(IACS),
 		.ROMCS(ROMCS),
 		.ROMCS4X(ROMCS4X),
 		.RAMCS(RAMCS),
 		.RAMCS0X(RAMCS0X),
-		.QoSCS(QoSCS),
-		.SndQoSCS(SndQoSCS));
+		/* Motherboard I/O device select outputs  */
+		.IACKCS(IACKCS),
+		.VIACS(VIACS),
+		.IWMCS(IWMCS),
+		.SCCCS(SCCCS),
+		.SCSICS(SCSICS),
+		.SndCSWR(SndCSWR),
+		/* Settings register select output */
+		.SetCSWR(SetCSWR));
 
 	wire RAMReady;
 	RAM ram(
@@ -196,7 +204,22 @@ module WarpSE(
 		.IOACT(IOACT),
 		.IODONE(IODONE));
 
-	wire SndQoSReady;
+	wire SlowIACK, SlowVIA, SlowIWM, SlowSCC, SlowSCSI, SlowSnd, SlowClockGate;
+	wire [3:0] SlowTimeout;
+	SET set(
+		.CLK(FCLK),
+		.BACT(BACT), 
+		.A(A_FSB[11:1]), 
+		.SetCSWR(SetCSWR),
+		.SlowIACK(SlowIACK),
+		.SlowVIA(SlowVIA),
+		.SlowIWM(SlowIWM),
+		.SlowSCC(SlowSCC),
+		.SlowSCSI(SlowSCSI),
+		.SlowSnd(SlowSnd),
+		.SlowClockGate(SlowClockGate),
+		.SlowTimeout(SlowTimeout));
+
 	wire nBR_IOBout;
 	assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
 	CNT cnt(
@@ -218,11 +241,23 @@ module WarpSE(
 		.nAS(nAS_FSB),
 		.ASrf(ASrf),
 		.BACT(BACT),
-		.QoSCS(QoSCS),
-		.SndQoSCS(SndQoSCS),
+		.IACKCS(IACKCS),
+		.VIACS(VIACS),
+		.IWMCS(IWMCS),
+		.SCCCS(SCCCS),
+		.SCSICS(SCSICS),
+		.SndCSWR(SndCSWR),
+		/* QoS settings inputs */
+		.SlowIACK(SlowIACK),
+		.SlowVIA(SlowVIA),
+		.SlowIWM(SlowIWM),
+		.SlowSCC(SlowSCC),
+		.SlowSCSI(SlowSCSI),
+		.SlowSnd(SlowSnd),
+		.SlowClockGate(SlowClockGate),
+		.SlowTimeout(SlowTimeout),
 		/* QoS outputs */
 		.QoSEN(QoSEN),
-		.SndQoSReady(SndQoSReady),
 		.MCKE(MCKE));
 	
 	FSB fsb(
@@ -243,9 +278,8 @@ module WarpSE(
 		.IOPWReady(IOPWReady),
 		.IONPReady(IONPReady),
 		.QoSEN(QoSEN),
-		.SndQoSReady(SndQoSReady),
 		/* Interrupt acknowledge select */
-		.IACS(IACS));
+		.IACKCS(IACKCS));
 
 
 endmodule