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0.7a-fastiack-fastscc-35us-noclockgate compiled

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This commit is contained in:
Zane Kaminski 2024-10-12 02:03:13 -04:00
parent 14557e03de
commit e5319295b0
42 changed files with 8223 additions and 3053 deletions
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2
cpld/SET.v
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@ -24,7 +24,7 @@ module SET(
SlowSCC <= 0;
SlowSCSI <= 1;
SlowSnd <= 1;
SlowClockGate <= 1;
SlowClockGate <= 0;
end else if (SetWRr) begin
SlowTimeout[3:0] <= A[11:8];
SlowIACK <= A[7];

5163
cpld/XC95144XL/WarpSE-0.7a-fastiack-fastscc-35us-noclockgate.svf Normal file
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File diff suppressed because it is too large Load Diff

2
cpld/XC95144XL/WarpSE.bld
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@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 154688 kilobytes
Total memory usage is 155072 kilobytes
Writing NGD file "WarpSE.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec

7
cpld/XC95144XL/WarpSE.cmd_log
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@ -1421,3 +1421,10 @@ XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
hprep6 -s IEEE1149 -n WarpSE -i WarpSE

12
cpld/XC95144XL/WarpSE.gise
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@ -70,7 +70,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1728712736" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728712728">
<transform xil_pn:end_ts="1728712929" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728712921">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -90,7 +90,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1728712741" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728712736">
<transform xil_pn:end_ts="1728712934" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728712929">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="WarpSE.bld"/>
@ -99,7 +99,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1728712760" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728712741">
<transform xil_pn:end_ts="1728712954" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728712934">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -119,12 +119,12 @@
<outfile xil_pn:name="WarpSE_html"/>
<outfile xil_pn:name="WarpSE_pad.csv"/>
</transform>
<transform xil_pn:end_ts="1728712778" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728712776">
<transform xil_pn:end_ts="1728712959" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728712957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="WarpSE.jed"/>
</transform>
<transform xil_pn:end_ts="1728712778" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728712778">
<transform xil_pn:end_ts="1728712959" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728712959">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_impactbatch.log"/>
@ -140,7 +140,7 @@
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1728712763" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728712760">
<transform xil_pn:end_ts="1728712956" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728712954">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>

16
cpld/XC95144XL/WarpSE.jed
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@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Sat Oct 12 01:59:36 2024
Date Extracted: Sat Oct 12 02:02:38 2024
QF93312*
QP100*
@ -427,7 +427,7 @@ L0019200 00000001 00000000 00000000 00000000 00000000 00000010 00000000 00000010
L0019264 00000000 00000000 00000000 00000010 00000010 00000001 00000000 00000010*
L0019328 00000001 00000000 00000001 00000011 00000010 00000010 00000000 00000010*
L0019392 00000000 00000000 00000001 00000010 00000000 00000001 00000001 00000000*
L0019456 00000001 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
L0019456 00000000 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
L0019520 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000*
L0019584 000000 000000 000000 000000 000000 000000 000000 000000*
L0019632 000000 001000 000000 000000 000000 100000 000000 000100*
@ -455,7 +455,7 @@ L0020800 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010
L0020864 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0020928 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0020992 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000001*
L0021056 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0021056 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0021120 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
L0021184 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
L0021248 00000000 00000000 00000010 00000000 00000000 00000001 00000000 00000000*
@ -470,7 +470,7 @@ L0021664 00000000 00000000 00000000 00001000 00000000 00001000 00000011 00000010
L0021728 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000010*
L0021792 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000000*
L0021856 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000*
L0021920 00000000 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
L0021920 00000100 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
L0021984 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0022048 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
L0022112 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
@ -1446,7 +1446,7 @@ L0077888 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000
L0077952 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000*
L0078016 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0078080 00000000 00000000 10000000 00000000 00000000 00000000 00000000 00000000*
L0078144 00000100 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
L0078144 00000000 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
L0078208 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0078272 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0078336 000000 000000 000000 000000 000000 000000 000000 000000*
@ -1461,7 +1461,7 @@ L0078752 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
L0078816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0078880 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0078944 00000000 00000000 00001000 00000000 00000000 00000000 00000000 00010000*
L0079008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
L0079008 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
L0079072 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
L0079136 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
L0079200 000000 000000 000000 000000 000001 000000 000000 000000*
@ -1710,5 +1710,5 @@ L0093120 000000 000000 000000 000000 000000 000010 010000 000000*
L0093168 000000 000000 000000 000000 000001 000000 000000 000000*
L0093216 000000 000000 000000 000000 000000 000000 000000 000000*
L0093264 000000 000000 000001 000000 000001 000000 000000 000000*
C4A76*
29D6
C49F6*
29DC

4
cpld/XC95144XL/WarpSE.mfd
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@ -575,8 +575,8 @@ INPUTS | 4 | nPOR | SlowClockGate | set/SetWRr | A_FSB<1>
INPUTMC | 3 | 0 | 17 | 0 | 16 | 6 | 3
INPUTP | 1 | 149
EQ | 3 |
!SlowClockGate.D = nPOR & !SlowClockGate & !set/SetWRr
# nPOR & !A_FSB<1> & set/SetWRr;
SlowClockGate.D = nPOR & SlowClockGate & !set/SetWRr
# nPOR & A_FSB<1> & set/SetWRr;
SlowClockGate.CLK = FCLK; // GCK
GLOBALS | 1 | 2 | FCLK

2
cpld/XC95144XL/WarpSE.nga
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2
cpld/XC95144XL/WarpSE.ngc
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2
cpld/XC95144XL/WarpSE.ngd
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2
cpld/XC95144XL/WarpSE.ngr
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2
cpld/XC95144XL/WarpSE.pad
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
10-12-2024 1:59AM
10-12-2024 2:02AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'

6
cpld/XC95144XL/WarpSE.rpt
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@ -1,7 +1,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: WarpSE Date: 10-12-2024, 1:59AM
Design Name: WarpSE Date: 10-12-2024, 2:02AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
@ -982,8 +982,8 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
RnW_IOB_OE <= NOT nAoutOE;
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
OR (nPOR AND A_FSB(1) AND set/SetWRr));
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)

14
cpld/XC95144XL/WarpSE.syr
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@ -4,7 +4,7 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst
@ -446,15 +446,15 @@ Design Statistics
# IOs : 80
Cell Usage :
# BELS : 687
# AND2 : 213
# BELS : 686
# AND2 : 214
# AND3 : 26
# AND4 : 13
# AND5 : 3
# AND8 : 2
# GND : 7
# INV : 274
# OR2 : 112
# INV : 273
# OR2 : 111
# OR3 : 10
# OR4 : 4
# OR5 : 1
@ -474,11 +474,11 @@ Cell Usage :
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.98 secs
Total CPU time to Xst completion: 5.14 secs
-->
Total memory usage is 263200 kilobytes
Total memory usage is 263136 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered)

5948
cpld/XC95144XL/WarpSE.vm6
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2
cpld/XC95144XL/WarpSE.xml
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BIN
cpld/XC95144XL/WarpSE_SVF.ipf
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Binary file not shown.

6
cpld/XC95144XL/WarpSE_html/fit/ascii.htm
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@ -3,7 +3,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: WarpSE Date: 10-12-2024, 1:59AM
Design Name: WarpSE Date: 10-12-2024, 2:02AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
@ -984,8 +984,8 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
RnW_IOB_OE <= NOT nAoutOE;
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
OR (nPOR AND A_FSB(1) AND set/SetWRr));
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)

4
cpld/XC95144XL/WarpSE_html/fit/defeqns.htm
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@ -218,8 +218,8 @@ FTCPE_RnW_IOB: FTCPE port map (RnW_IOB_I,RnW_IOB_T,NOT C16M,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RnW_IOB_OE <= NOT nAoutOE;
</td></tr><tr><td>
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nPOR AND A_FSB(1) AND set/SetWRr));
</td></tr><tr><td>
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)

6
cpld/XC95144XL/WarpSE_html/fit/eqns.htm
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@ -4,7 +4,7 @@
var design = "WarpSE";
var device = "XC95144XL";
signals = new Array("ALE0M","ALE0S","ASrf","BACTr","GA22_SPECSIG","GA23_SPECSIG","IOACT","IODONE","IOL0","IONPReady","IOREQ","IORW","IOU0","MCKE","QoSEN","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RAMReady","RefReq","RefUrg","RnW_IOB","SlowClockGate","SlowIACK","SlowIWM","SlowSCC","SlowSCSI","SlowSnd","SlowTimeout0_SPECSIG","SlowTimeout1_SPECSIG","SlowTimeout2_SPECSIG","SlowTimeout3_SPECSIG","SlowVIA","cntC8Mr0_SPECSIG","cntC8Mr1_SPECSIG","cntC8Mr2_SPECSIG","cntC8Mr3_SPECSIG","cntEr0_SPECSIG","cntEr1_SPECSIG","cntIS0_SPECSIG","cntIS1_SPECSIG","cntLTimer0_SPECSIG","cntLTimer10_SPECSIG","cntLTimer11_SPECSIG","cntLTimer1_SPECSIG","cntLTimer2_SPECSIG","cntLTimer3_SPECSIG","cntLTimer4_SPECSIG","cntLTimer5_SPECSIG","cntLTimer6_SPECSIG","cntLTimer7_SPECSIG","cntLTimer8_SPECSIG","cntLTimer9_SPECSIG","cntLTimerTick_SPECSIG","cntQS0_SPECSIG","cntQS1_SPECSIG","cntQS2_SPECSIG","cntQS3_SPECSIG","cntQoSCSr_SPECSIG","cntTimer0_SPECSIG","cntTimer1_SPECSIG","cntTimer2_SPECSIG","cntTimer3_SPECSIG","cntTimerTick_SPECSIG","csOverlay_SPECSIG","iobmC8Mr_SPECSIG","iobmDoutOE_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmIOS_FSM_FFd5_SPECSIG","iobmIOS_FSM_FFd6_SPECSIG","iobmIOS_FSM_FFd7_SPECSIG","iobmVPAr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIODONEr0_SPECSIG","iobsIODONEr1_SPECSIG","iobsIODONErf_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsSent_SPECSIG","iobsTS_FSM_FFd1_SPECSIG","iobsTS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nBR_IOB","nBR_IOBout","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nPOR","nRAMLWE","nRAMUWE","nRAS","nRES","nRESout","nROMOE","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramCASEndEN_SPECSIG","ramRASEL_SPECSIG","ramRASEN_SPECSIG","ramRASrf_SPECSIG","ramRS0_SPECSIG","ramRS1_SPECSIG","ramRS2_SPECSIG","ramRefCAS_SPECSIG","ramRefDone_SPECSIG","setSetWRr_SPECSIG");
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","OFF","ON","OFF","ON","ON","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","ON","OFF","ON","ON","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
sigTypes = new Array("D","D","D","D","","","D","D","D","D","D","D","D","D","D","","","","","","","","","","","","","D","D","D","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","T","T","T","T","T","T","T","T","T","T","T","T","D","D","D","T","D","D","T","T","T","T","D","T","D","D","T","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","D","T","D","D","","D","D","D","T","","D","D","D","D","","","D","D","T","","","","","D","","","D","T","D","D","D","D","D","D","T","T","D","D","D");
@ -292,9 +292,9 @@
pterms["FB1_16_2"]=new Array("nPOR","A_FSB7_SPECSIG","setSetWRr_SPECSIG");
pterms["FB1_17_1"]=new Array("nPOR","/SlowClockGate","/setSetWRr_SPECSIG");
pterms["FB1_17_1"]=new Array("nPOR","SlowClockGate","/setSetWRr_SPECSIG");
pterms["FB1_17_2"]=new Array("nPOR","/A_FSB1_SPECSIG","setSetWRr_SPECSIG");
pterms["FB1_17_2"]=new Array("nPOR","A_FSB1_SPECSIG","setSetWRr_SPECSIG");
pterms["FB1_18_1"]=new Array("/nPOR","/cntC8Mr1_SPECSIG","cntC8Mr0_SPECSIG");

2
cpld/XC95144XL/WarpSE_html/fit/summary.htm
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@ -30,7 +30,7 @@
<tr>
<td width="40%"> <b>Date</b>
</td>
<td width="60%"> 10-12-2024, 1:59AM</td>
<td width="60%"> 10-12-2024, 2:02AM</td>
</tr>
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">

4
cpld/XC95144XL/WarpSE_html/tim/timing_report.htm
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@ -27,7 +27,7 @@
<TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC95144XL</A>, -10 (3.0)</TD>
</TR>
<TR>
<TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 01:59:21 2024
<TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 02:02:35 2024
</TD>
</TR>
<TR>
@ -3882,7 +3882,7 @@ function AUTO_TS_F2P_BACTr_Q_to_nDinOE() {
<SPAN CLASS="cpldta_text_normal">809</SPAN>
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of Timing errors:</B></SPAN>
<SPAN CLASS="cpldta_text_normal">809</SPAN>
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 01:59:21 2024
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 02:02:35 2024
</SPAN>
<HR>
</HTML>

14
cpld/XC95144XL/WarpSE_ngdbuild.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sat Oct 12 01:59:00 2024">
<application stringID="NgdBuild" timeStamp="Sat Oct 12 02:02:13 2024">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -66,7 +66,7 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="213"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="214"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
@ -76,24 +76,24 @@
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="274"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="273"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="111"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="21"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="213"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="214"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="72"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="43"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="274"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="273"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="111"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>

2
cpld/XC95144XL/WarpSE_pad.csv
View File

@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
10-12-2024 1:59AM
10-12-2024 2:02AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','

1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 10-12-2024 1:59AM 10-12-2024 2:02AM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.

10
cpld/XC95144XL/WarpSE_summary.html
View File

@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 01:59:38)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 02:02:39)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD>
@ -65,9 +65,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 01:58:54 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 01:59:00 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 01:59:14 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:02:08 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:02:13 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 02:02:28 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 10/12/2024 - 01:59:38</center>
<br><center><b>Date Generated:</b> 10/12/2024 - 02:02:39</center>
</BODY></HTML>

10
cpld/XC95144XL/WarpSE_xst.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Oct 12 01:58:49 2024">
<application stringID="Xst" timeStamp="Sat Oct 12 02:02:03 2024">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -118,13 +118,13 @@
<item stringID="XST_IOS" value="80"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="687">
<item dataType="int" stringID="XST_AND2" value="213"/>
<item dataType="int" stringID="XST_BELS" value="686">
<item dataType="int" stringID="XST_AND2" value="214"/>
<item dataType="int" stringID="XST_AND3" value="26"/>
<item dataType="int" stringID="XST_AND4" value="13"/>
<item dataType="int" stringID="XST_GND" value="7"/>
<item dataType="int" stringID="XST_INV" value="274"/>
<item dataType="int" stringID="XST_OR2" value="112"/>
<item dataType="int" stringID="XST_INV" value="273"/>
<item dataType="int" stringID="XST_OR2" value="111"/>
<item dataType="int" stringID="XST_XOR2" value="21"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="113">

2
cpld/XC95144XL/_ngo/netlist.lst
View File

@ -1,2 +1,2 @@
C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728712734
C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728712928
OK

2
cpld/XC95144XL/iseconfig/WarpSE.xreport
View File

@ -1,7 +1,7 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2024-10-12T01:58:40</DateModified>
<DateModified>2024-10-12T02:01:52</DateModified>
<ModuleName>WarpSE</ModuleName>
<SummaryTimeStamp>2024-10-09T06:57:43</SummaryTimeStamp>
<SavedFilePath>C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>

4
cpld/XC95144XL/usage_statistics_webtalk.html
View File

@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">1b61e5067b04455196399c35c956f18d</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">4358b7a1369742b983bb46cda94c943f</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage"></xtag-property></TD>
</TR>
@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2024-10-12T02:01:02</xtag-property></TD>
<TD><xtag-property name="Date Generated">2024-10-12T02:03:05</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">IMPACT</xtag-property></TD>
</TR>

2
cpld/XC95144XL/webtalk.log
View File

@ -3,7 +3,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=1b61e5067b04455196399c35c956f18d
ProjectID=4358b7a1369742b983bb46cda94c943f
ProjectIteration=1
WebTalk Summary

4
cpld/XC95144XL/webtalk_impact.xml
View File

@ -3,9 +3,9 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="impact" timeStamp="Sat Oct 12 02:01:02 2024">
<application name="impact" timeStamp="Sat Oct 12 02:03:04 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="1b61e5067b04455196399c35c956f18d"/>
<property name="ProjectID" value="4358b7a1369742b983bb46cda94c943f"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">

2
cpld/XC95144XL/webtalk_pn.xml
View File

@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Oct 12 01:58:48 2024">
<application name="pn" timeStamp="Sat Oct 12 02:02:02 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="B70E14F6F6B943E9BF9FD5113EA04D70" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>

BIN
cpld/XC95144XL/xlnx_auto_0_xdb/cst.xbcd
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16
cpld/XC95144XL/xst/work/hdllib.ref
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@ -1,8 +1,8 @@
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728712730
MO CS NULL ../CS.v vlg22/_c_s.bin 1728712730
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728712730
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728712730
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728712730
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728712730
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728712730
MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728712730
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728712923
MO CS NULL ../CS.v vlg22/_c_s.bin 1728712923
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728712923
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728712923
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728712923
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728712923
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728712923
MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728712923

BIN
cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin
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BIN
cpld/XC95144XL/xst/work/vlg22/_c_s.bin
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BIN
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BIN
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BIN
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cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
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cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin
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cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin
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