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Warp-SE
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This commit is contained in:
Zane Kaminski 2022-02-16 08:18:41 -05:00
parent b03c9871f2
commit e680385b1e
52 changed files with 191180 additions and 4483 deletions
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4
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@ -1486,8 +1486,8 @@
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22
DIPSW.kicad_sch
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@ -149,11 +149,11 @@
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112
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(property "Reference" "#PWR0128" (id 0) (at 181.61 99.06 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "+3V3" (id 1) (at 80.01 109.22 0))
(property "Footprint" "" (id 2) (at 80.01 113.03 0)
(property "Value" "+3V3" (id 1) (at 181.61 91.44 0))
(property "Footprint" "" (id 2) (at 181.61 95.25 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 80.01 113.03 0)
(property "Datasheet" "" (id 3) (at 181.61 95.25 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid deb9ebef-314a-4c99-adb7-ab285004007d))
@ -1535,17 +1535,17 @@
(pin "1" (uuid df6cfdb3-2a8b-40a4-b77f-46c3a2ec7231))
)
(symbol (lib_id "power:GND") (at 77.47 125.73 0) (unit 1)
(symbol (lib_id "power:GND") (at 179.07 107.95 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-000061e4a7db)
(property "Reference" "#PWR0127" (id 0) (at 77.47 132.08 0)
(property "Reference" "#PWR0127" (id 0) (at 179.07 114.3 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 77.47 129.54 0))
(property "Footprint" "" (id 2) (at 77.47 125.73 0)
(property "Value" "GND" (id 1) (at 179.07 111.76 0))
(property "Footprint" "" (id 2) (at 179.07 107.95 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 77.47 125.73 0)
(property "Datasheet" "" (id 3) (at 179.07 107.95 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 67253a3e-10e5-4396-a563-bb3ce5146e90))
@ -1617,17 +1617,17 @@
(pin "6" (uuid a0d3c320-f882-4c60-809b-3dc09f9b126c))
)
(symbol (lib_id "power:GND") (at 82.55 115.57 0) (unit 1)
(symbol (lib_id "power:GND") (at 184.15 97.79 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-000061e5e60d)
(property "Reference" "#PWR0204" (id 0) (at 82.55 121.92 0)
(property "Reference" "#PWR0204" (id 0) (at 184.15 104.14 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 82.55 119.38 0))
(property "Footprint" "" (id 2) (at 82.55 115.57 0)
(property "Value" "GND" (id 1) (at 184.15 101.6 0))
(property "Footprint" "" (id 2) (at 184.15 97.79 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 82.55 115.57 0)
(property "Datasheet" "" (id 3) (at 184.15 97.79 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid f8c98054-7416-44eb-b452-6f525fbc9852))
@ -1923,77 +1923,77 @@
(pin "1" (uuid 1bddb37d-e0ab-497e-9d03-a79e3b52bd60))
)
(symbol (lib_id "Device:R_Small") (at 111.76 106.68 0) (mirror y) (unit 1)
(symbol (lib_id "Device:R_Small") (at 143.51 106.68 0) (mirror y) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-0000627624e5)
(property "Reference" "R16" (id 0) (at 113.03 105.41 0)
(property "Reference" "R16" (id 0) (at 144.78 105.41 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Value" "10k" (id 1) (at 113.03 107.95 0)
(property "Value" "10k" (id 1) (at 144.78 107.95 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Footprint" "stdpads:R_0603" (id 2) (at 111.76 106.68 0)
(property "Footprint" "stdpads:R_0603" (id 2) (at 143.51 106.68 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 111.76 106.68 0)
(property "Datasheet" "~" (id 3) (at 143.51 106.68 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "LCSC Part" "C25804" (id 4) (at 111.76 106.68 0)
(property "LCSC Part" "C25804" (id 4) (at 143.51 106.68 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 1c398a39-9517-4d77-86fd-5610ce8bd0a7))
(pin "2" (uuid c80621c4-81c7-4209-97a8-6143c833b7eb))
)
(symbol (lib_id "Device:R_Small") (at 111.76 99.06 0) (mirror y) (unit 1)
(symbol (lib_id "Device:R_Small") (at 143.51 99.06 0) (mirror y) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-000062762b96)
(property "Reference" "R15" (id 0) (at 113.03 97.79 0)
(property "Reference" "R15" (id 0) (at 144.78 97.79 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Value" "10k" (id 1) (at 113.03 100.33 0)
(property "Value" "10k" (id 1) (at 144.78 100.33 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Footprint" "stdpads:R_0603" (id 2) (at 111.76 99.06 0)
(property "Footprint" "stdpads:R_0603" (id 2) (at 143.51 99.06 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 111.76 99.06 0)
(property "Datasheet" "~" (id 3) (at 143.51 99.06 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "LCSC Part" "C25804" (id 4) (at 111.76 99.06 0)
(property "LCSC Part" "C25804" (id 4) (at 143.51 99.06 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid bd9971c7-421a-4318-8d59-c82dfeb65b2c))
(pin "2" (uuid cde28874-0011-4849-87a9-ffea5714b93b))
)
(symbol (lib_id "power:+3V3") (at 111.76 96.52 0) (unit 1)
(symbol (lib_id "power:+3V3") (at 143.51 96.52 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-00006276b755)
(property "Reference" "#PWR0205" (id 0) (at 111.76 100.33 0)
(property "Reference" "#PWR0205" (id 0) (at 143.51 100.33 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "+3V3" (id 1) (at 111.76 92.71 0))
(property "Footprint" "" (id 2) (at 111.76 96.52 0)
(property "Value" "+3V3" (id 1) (at 143.51 92.71 0))
(property "Footprint" "" (id 2) (at 143.51 96.52 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 111.76 96.52 0)
(property "Datasheet" "" (id 3) (at 143.51 96.52 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 293e44db-de95-47ed-9bed-4003e28d7566))
)
(symbol (lib_id "power:GND") (at 111.76 109.22 0) (unit 1)
(symbol (lib_id "power:GND") (at 143.51 109.22 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-00006276bbe6)
(property "Reference" "#PWR0206" (id 0) (at 111.76 115.57 0)
(property "Reference" "#PWR0206" (id 0) (at 143.51 115.57 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 111.76 113.03 0))
(property "Footprint" "" (id 2) (at 111.76 109.22 0)
(property "Value" "GND" (id 1) (at 143.51 113.03 0))
(property "Footprint" "" (id 2) (at 143.51 109.22 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 111.76 109.22 0)
(property "Datasheet" "" (id 3) (at 143.51 109.22 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid dc8f2e78-bb60-4b23-aa67-dab0fc15d059))

106
RAMROM.kicad_sch
View File

@ -439,21 +439,27 @@
(junction (at 265.43 111.76) (diameter 0) (color 0 0 0 0)
(uuid 24fbbd33-4896-414c-ba79-167809dd0e90)
)
(junction (at 265.43 106.68) (diameter 0) (color 0 0 0 0)
(uuid 54ea3c91-f824-4ee5-a744-4634dc7b3e93)
)
(junction (at 115.57 115.57) (diameter 0) (color 0 0 0 0)
(uuid 557d128f-cf69-4c70-9959-d139ac95c63c)
)
(junction (at 146.05 120.65) (diameter 0) (color 0 0 0 0)
(uuid 7c0eaeb4-40a6-4f67-a3f8-d33c563c85f8)
)
(junction (at 255.27 106.68) (diameter 0) (color 0 0 0 0)
(uuid 7ca09fd4-d48a-436a-8dbe-2bf5119efecb)
)
(junction (at 125.73 115.57) (diameter 0) (color 0 0 0 0)
(uuid 856c0384-2dfc-47d2-a66c-a145c3149f14)
)
(junction (at 146.05 120.65) (diameter 0) (color 0 0 0 0)
(uuid 9cdaf74c-bd9d-4293-9612-c30a4bca9a30)
)
(junction (at 135.89 120.65) (diameter 0) (color 0 0 0 0)
(uuid cad44c02-7fd2-4e9a-b93a-e1b73d6a3ee6)
)
(junction (at 275.59 111.76) (diameter 0) (color 0 0 0 0)
(uuid da8cef22-8613-4e08-9b41-406c689b1603)
)
(junction (at 125.73 120.65) (diameter 0) (color 0 0 0 0)
(uuid e47d9cf3-579e-4750-bc6d-bf58b55862bb)
)
@ -934,6 +940,10 @@
(uuid 24381631-d76d-44b8-abc0-1b9b665369c8)
)
(wire (pts (xy 265.43 106.68) (xy 275.59 106.68))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 27d84b5d-9e97-494c-b6ba-07ac346905f2)
)
(wire (pts (xy 210.82 55.88) (xy 205.74 55.88))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2a507df7-40c5-4523-b0fd-269cea55efb9)
@ -1286,6 +1296,10 @@
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 92786ddd-53cc-4458-af25-eb5a2b46154e)
)
(wire (pts (xy 265.43 111.76) (xy 275.59 111.76))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 93579848-3c8e-40db-a11f-27e2944f5ed1)
)
(bus (pts (xy 203.2 71.12) (xy 203.2 76.2))
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9379168f-48ca-4895-ae2a-f80925ada292)
@ -2316,22 +2330,6 @@
(pin "2" (uuid 3da133a0-900a-419b-919b-b0b8cf353a10))
)
(symbol (lib_id "power:GND") (at 146.05 120.65 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-00006160c7cd)
(property "Reference" "#PWR0135" (id 0) (at 146.05 127 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 146.05 124.46 0))
(property "Footprint" "" (id 2) (at 146.05 120.65 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 146.05 120.65 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 6b9b9715-1fbf-4008-978a-8bc6b930f72b))
)
(symbol (lib_id "GW_RAM:Flash-512Kx8-PLCC-32") (at 220.98 58.42 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-000061871415)
@ -2520,22 +2518,6 @@
(pin "2" (uuid 8f714d20-b486-4831-baaa-dd093fd82fd1))
)
(symbol (lib_id "power:GND") (at 265.43 111.76 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-0000618714ee)
(property "Reference" "#PWR0200" (id 0) (at 265.43 118.11 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 265.43 115.57 0))
(property "Footprint" "" (id 2) (at 265.43 111.76 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 265.43 111.76 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 0bb047bb-c679-4bfc-b861-9203dafc1b5e))
)
(symbol (lib_id "power:+5V") (at 97.79 67.31 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-000061aab186)
@ -2599,4 +2581,58 @@
)
(pin "1" (uuid d590efe6-8b8a-49ca-a2b8-1c8b75eb0589))
)
(symbol (lib_id "power:GND") (at 275.59 111.76 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 98a835a6-2a9b-4a90-9b44-451f01d50d0c)
(property "Reference" "#PWR0135" (id 0) (at 275.59 118.11 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 275.59 115.57 0))
(property "Footprint" "" (id 2) (at 275.59 111.76 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 275.59 111.76 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 83aa4115-5bca-4460-a562-34a231149c34))
)
(symbol (lib_id "Device:C_Small") (at 275.59 109.22 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid acb3f20b-1e4f-49e8-a1e8-45784e27e149)
(property "Reference" "C45" (id 0) (at 276.86 107.95 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "10u" (id 1) (at 276.86 110.49 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "stdpads:C_0805" (id 2) (at 275.59 109.22 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 275.59 109.22 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "LCSC Part" "C15850" (id 4) (at 275.59 109.22 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid b9daff3e-fb8a-4fdd-999c-dfc98923ebf1))
(pin "2" (uuid c2cedebd-33c7-4889-9977-33f1c49e5e6f))
)
(symbol (lib_id "power:GND") (at 146.05 120.65 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid c7ccb402-2065-48b9-b3c6-8970af29b229)
(property "Reference" "#PWR0157" (id 0) (at 146.05 127 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "GND" (id 1) (at 146.05 124.46 0))
(property "Footprint" "" (id 2) (at 146.05 120.65 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 146.05 120.65 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid d80dcff9-10e2-49a6-a256-1e79e51db9dc))
)
)

186016
Warp-SE.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

16
Warp-SE.kicad_sch
View File

@ -1308,8 +1308,8 @@
(path "/00000000-0000-0000-0000-000061350d21/00000000-0000-0000-0000-000061bf038c"
(reference "#PWR0114") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-000061a87b62/00000000-0000-0000-0000-00006279fb2c"
(reference "#PWR0115") (unit 1) (value "+5V") (footprint "")
(path "/00000000-0000-0000-0000-000061a87b62/4909eb18-dc20-4813-9983-1452e243ca71"
(reference "#PWR0115") (unit 1) (value "+3V3") (footprint "")
)
(path "/00000000-0000-0000-0000-000061350d21/00000000-0000-0000-0000-000061bf0398"
(reference "#PWR0116") (unit 1) (value "+3V3") (footprint "")
@ -1368,7 +1368,7 @@
(path "/00000000-0000-0000-0000-00005f723900/00000000-0000-0000-0000-0000614735f4"
(reference "#PWR0134") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005f723900/00000000-0000-0000-0000-00006160c7cd"
(path "/00000000-0000-0000-0000-00005f723900/98a835a6-2a9b-4a90-9b44-451f01d50d0c"
(reference "#PWR0135") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-000061b3a5f1/00000000-0000-0000-0000-000061b42970"
@ -1434,8 +1434,8 @@
(path "/00000000-0000-0000-0000-00005f6da71d/00000000-0000-0000-0000-000061704865"
(reference "#PWR0156") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005f6da71d/00000000-0000-0000-0000-00006170b699"
(reference "#PWR0157") (unit 1) (value "+5V") (footprint "")
(path "/00000000-0000-0000-0000-00005f723900/c7ccb402-2065-48b9-b3c6-8970af29b229"
(reference "#PWR0157") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005f723173/00000000-0000-0000-0000-0000616131f5"
(reference "#PWR0158") (unit 1) (value "+3V3") (footprint "")
@ -1557,9 +1557,6 @@
(path "/00000000-0000-0000-0000-000061aa52c4/00000000-0000-0000-0000-000061f58615"
(reference "#PWR0199") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005f723900/00000000-0000-0000-0000-0000618714ee"
(reference "#PWR0200") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-000061aa52c4/00000000-0000-0000-0000-000061d388d3"
(reference "#PWR0202") (unit 1) (value "+3V3") (footprint "")
)
@ -1704,6 +1701,9 @@
(path "/00000000-0000-0000-0000-000060941922/00000000-0000-0000-0000-0000616280b5"
(reference "C44") (unit 1) (value "2u2") (footprint "stdpads:C_0603")
)
(path "/00000000-0000-0000-0000-00005f723900/acb3f20b-1e4f-49e8-a1e8-45784e27e149"
(reference "C45") (unit 1) (value "10u") (footprint "stdpads:C_0805")
)
(path "/00000000-0000-0000-0000-000061aa52c4/00000000-0000-0000-0000-000061e5e607"
(reference "C46") (unit 1) (value "22p") (footprint "stdpads:C_0603")
)

2
cpld/RAM.v
View File

@ -34,7 +34,7 @@ module RAM(
assign RA[11] = A[19];
assign RA[10] = A[21];
assign RA[09] = RASEL ? A[20] : A[19];
assign RA[08] = (RASEL && RAMSEL) ? A[09] : A[18];
assign RA[08] = (RASEL && RAMCS) ? A[09] : A[18];
assign RA[07] = RASEL ? A[08] : A[17];
assign RA[06] = RASEL ? A[07] : A[16];
assign RA[05] = RASEL ? A[06] : A[15];

4
cpld/XC95144XL/MXSE.bld
View File

@ -28,10 +28,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 117492 kilobytes
Total memory usage is 117236 kilobytes
Writing NGD file "MXSE.ngd" ...
Total REAL time to NGDBUILD completion: 18 sec
Total REAL time to NGDBUILD completion: 17 sec
Total CPU time to NGDBUILD completion: 17 sec
Writing NGDBUILD log file "MXSE.bld"...

11
cpld/XC95144XL/MXSE.cmd_log
View File

@ -8,3 +8,14 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess MXSE_build.xml
tsim -intstyle ise MXSE MXSE.nga
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
xst -intstyle ise -ifn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.xst" -ofn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.syr"
xst -intstyle ise -ifn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.xst" -ofn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.syr"
xst -intstyle ise -ifn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.xst" -ofn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.syr"
xst -intstyle ise -ifn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.xst" -ofn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.syr"
xst -intstyle ise -ifn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.xst" -ofn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.syr"
xst -intstyle ise -ifn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.xst" -ofn "//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/MXSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc //192.168.64.1/Repos/Warp-SE/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
XSLTProcess MXSE_build.xml
tsim -intstyle ise MXSE MXSE.nga
hprep6 -s IEEE1149 -n MXSE -i MXSE

4
cpld/XC95144XL/MXSE.gyd
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@ -77,7 +77,7 @@ PARTITION FB1_1 iobs/IOACTr iobm/IOREQr iobm/Er2 iobm/DTACKrr
iobm/DTACKrf iobm/BERRrr iobm/BERRrf fsb/ASrf
cnt/RefCnt<7> cnt/RefCnt<6> cnt/RefCnt<5> cnt/RefCnt<4>
cnt/RefCnt<3> cnt/RefCnt<2> cnt/RefCnt<1> cnt/RefCnt<0>
RefAck $OpTx$FX_DC$607
RefAck $OpTx$FX_DC$609
PARTITION FB2_14 iobm/VPArr iobm/VPArf iobm/RESrr iobm/RESrf
iobm/Er
PARTITION FB3_1 EXP14_ fsb/VPA EXP15_ EXP16_
@ -88,7 +88,7 @@ PARTITION FB3_1 EXP14_ fsb/VPA EXP15_ EXP16_
PARTITION FB4_1 ram/BACTr nAoutOE_OBUF iobs/Clear1 ALE0S
nDoutOE_OBUF nDinOE_OBUF iobs/PS_FSM_FFd1 iobs/IOU1
iobs/IOL1 iobm/IOS_FSM_FFd2 nVPA_FSB_OBUF iobm/IOS_FSM_FFd1
fsb/BERR1r cs/nOverlay1 $OpTx$FX_DC$608 IOU0
fsb/BERR1r cs/nOverlay1 $OpTx$FX_DC$610 IOU0
IOL0 iobs/IOReady
PARTITION FB5_1 EXP26_ nROMCS_OBUF EXP27_ iobs/PS_FSM_FFd2
nCAS_OBUF nOE_OBUF EXP28_ iobs/Once

1714
cpld/XC95144XL/MXSE.jed Normal file
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File diff suppressed because it is too large Load Diff

204
cpld/XC95144XL/MXSE.mfd
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@ -15,7 +15,7 @@ GLOBALS | 1 | 2 | CLK2X_IOB
MACROCELL | 3 | 13 | cs/nOverlay1
ATTRIBUTES | 8553280 | 0
OUTPUTMC | 40 | 7 | 6 | 4 | 6 | 4 | 13 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 0 | 2 | 11 | 7 | 11 | 2 | 7 | 6 | 16 | 6 | 14 | 7 | 3 | 6 | 11 | 4 | 2 | 7 | 7 | 4 | 11 | 7 | 13 | 6 | 17 | 7 | 4 | 4 | 1 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 0 | 4 | 4 | 4 | 5 | 6 | 13 | 7 | 1 | 7 | 9 | 7 | 12 | 7 | 15 | 7 | 16 | 7 | 17
OUTPUTMC | 43 | 7 | 6 | 4 | 6 | 4 | 13 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 0 | 2 | 11 | 7 | 11 | 2 | 7 | 6 | 16 | 6 | 14 | 7 | 3 | 6 | 11 | 4 | 2 | 7 | 7 | 4 | 11 | 7 | 13 | 6 | 17 | 6 | 7 | 7 | 4 | 4 | 1 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 0 | 4 | 4 | 4 | 5 | 6 | 6 | 6 | 8 | 6 | 13 | 7 | 1 | 7 | 9 | 7 | 12 | 7 | 15 | 7 | 16 | 7 | 17
INPUTS | 3 | cs/nOverlay0 | nAS_FSB | fsb/ASrf
INPUTMC | 2 | 6 | 6 | 0 | 7
INPUTP | 1 | 54
@ -183,17 +183,20 @@ GLOBALS | 1 | 2 | CLK_FSB
MACROCELL | 6 | 6 | cs/nOverlay0
ATTRIBUTES | 4358928 | 0
OUTPUTMC | 2 | 3 | 13 | 6 | 6
INPUTS | 8 | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | cs/nOverlay0 | nAS_FSB | fsb/ASrf | nRES
INPUTMC | 2 | 6 | 6 | 0 | 7
INPUTP | 6 | 36 | 30 | 29 | 28 | 54 | 145
EQ | 6 |
OUTPUTMC | 3 | 3 | 13 | 6 | 6 | 6 | 7
INPUTS | 11 | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | cs/nOverlay0 | nAS_FSB | fsb/ASrf | nRES | A_FSB<9> | cs/nOverlay1 | ram/RASEL
INPUTMC | 4 | 6 | 6 | 0 | 7 | 3 | 13 | 7 | 0
INPUTP | 7 | 36 | 30 | 29 | 28 | 54 | 145 | 12
EXPORTS | 1 | 6 | 7
EQ | 8 |
cs/nOverlay0.T = !A_FSB<23> & A_FSB<22> & !A_FSB<21> & !A_FSB<20> &
!cs/nOverlay0 & !nAS_FSB
# !A_FSB<23> & A_FSB<22> & !A_FSB<21> & !A_FSB<20> &
!cs/nOverlay0 & fsb/ASrf;
cs/nOverlay0.CLK = CLK_FSB; // GCK
cs/nOverlay0.AR = !nRES;
cs/nOverlay0.EXP = A_FSB<9> & !A_FSB<23> & !A_FSB<22> & cs/nOverlay1 &
ram/RASEL
GLOBALS | 1 | 2 | CLK_FSB
MACROCELL | 3 | 16 | IOL0
@ -421,99 +424,99 @@ GLOBALS | 1 | 2 | CLK_FSB
MACROCELL | 2 | 1 | fsb/VPA
ATTRIBUTES | 8553216 | 0
OUTPUTMC | 6 | 2 | 1 | 3 | 10 | 2 | 0 | 2 | 2 | 2 | 3 | 2 | 17
INPUTS | 10 | fsb/BERR1r | fsb/VPA | $OpTx$FX_DC$607 | BERR_IOBS | fsb/BERR0r | A_FSB<20> | TimeoutB | A_FSB<23> | EXP14_.EXP | EXP15_.EXP
INPUTS | 10 | fsb/BERR1r | fsb/VPA | $OpTx$FX_DC$609 | BERR_IOBS | fsb/BERR0r | A_FSB<20> | TimeoutB | A_FSB<23> | EXP14_.EXP | EXP15_.EXP
INPUTMC | 8 | 3 | 12 | 2 | 1 | 0 | 17 | 4 | 15 | 7 | 2 | 6 | 0 | 2 | 0 | 2 | 2
INPUTP | 2 | 28 | 36
IMPORTS | 2 | 2 | 0 | 2 | 2
EQ | 89 |
fsb/VPA.D = BERR_IOBS & fsb/VPA & !$OpTx$FX_DC$607
# fsb/BERR0r & fsb/VPA & !$OpTx$FX_DC$607
# fsb/BERR1r & fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA.D = BERR_IOBS & fsb/VPA & !$OpTx$FX_DC$609
# fsb/BERR0r & fsb/VPA & !$OpTx$FX_DC$609
# fsb/BERR1r & fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<23> & TimeoutB & fsb/VPA &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# !A_FSB<20> & TimeoutB & fsb/VPA &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
;Imported pterms FB3_1
# !A_FSB<22> & TimeoutB & fsb/VPA &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# A_FSB<21> & TimeoutB & fsb/VPA &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# A_FSB<23> & !fsb/Ready1r & fsb/VPA &
!iobs/IOReady & !$OpTx$FX_DC$607
!iobs/IOReady & !$OpTx$FX_DC$609
# !A_FSB<23> & !A_FSB<22> & cs/nOverlay1 &
!fsb/Ready0r & fsb/VPA & !ram/RAMReady & !$OpTx$FX_DC$607
!fsb/Ready0r & fsb/VPA & !ram/RAMReady & !$OpTx$FX_DC$609
# A_FSB<22> & !A_FSB<21> & A_FSB<20> & !fsb/Ready1r &
fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$607
fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$609
;Imported pterms FB3_18
# A_FSB<9> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
;Imported pterms FB3_3
# !A_FSB<23> & A_FSB<22> & A_FSB<21> &
!cs/nOverlay1 & !fsb/Ready0r & fsb/VPA & !ram/RAMReady &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# A_FSB<14> & A_FSB<22> & A_FSB<20> & A_FSB<19> &
A_FSB<18> & A_FSB<17> & A_FSB<16> & !cs/nOverlay1 & !nWE_FSB &
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$607
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$609
# A_FSB<13> & A_FSB<22> & A_FSB<20> & A_FSB<19> &
A_FSB<18> & A_FSB<17> & A_FSB<16> & !cs/nOverlay1 & !nWE_FSB &
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$607
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$609
# A_FSB<14> & !A_FSB<22> & A_FSB<21> & A_FSB<20> &
A_FSB<19> & A_FSB<18> & A_FSB<17> & A_FSB<16> &
cs/nOverlay1 & !nWE_FSB & !fsb/Ready1r & fsb/VPA & !iobs/IOReady &
!nADoutLE1 & !$OpTx$FX_DC$607
!nADoutLE1 & !$OpTx$FX_DC$609
# A_FSB<13> & !A_FSB<22> & A_FSB<21> & A_FSB<20> &
A_FSB<19> & A_FSB<18> & A_FSB<17> & A_FSB<16> &
cs/nOverlay1 & !nWE_FSB & !fsb/Ready1r & fsb/VPA & !iobs/IOReady &
!nADoutLE1 & !$OpTx$FX_DC$607
!nADoutLE1 & !$OpTx$FX_DC$609
;Imported pterms FB3_4
# A_FSB<9> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !TimeoutB & !fsb/BERR0r &
!fsb/BERR1r & fsb/Ready1r & !$OpTx$FX_DC$607
!fsb/BERR1r & fsb/Ready1r & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !TimeoutB & !fsb/BERR0r &
!fsb/BERR1r & iobs/IOReady & !$OpTx$FX_DC$607;
!fsb/BERR1r & iobs/IOReady & !$OpTx$FX_DC$609;
fsb/VPA.CLK = CLK_FSB; // GCK
GLOBALS | 1 | 2 | CLK_FSB
@ -634,7 +637,7 @@ GLOBALS | 1 | 2 | CLK_FSB
MACROCELL | 2 | 8 | nDTACK_FSB_OBUF
ATTRIBUTES | 8815362 | 0
OUTPUTMC | 5 | 2 | 8 | 2 | 6 | 2 | 7 | 2 | 9 | 2 | 10
INPUTS | 9 | fsb/BERR1r | nDTACK_FSB | BERR_IOBS | fsb/BERR0r | $OpTx$FX_DC$608 | nAS_FSB | fsb/ASrf | EXP19_.EXP | EXP20_.EXP
INPUTS | 9 | fsb/BERR1r | nDTACK_FSB | BERR_IOBS | fsb/BERR0r | $OpTx$FX_DC$610 | nAS_FSB | fsb/ASrf | EXP19_.EXP | EXP20_.EXP
INPUTMC | 8 | 3 | 12 | 2 | 8 | 4 | 15 | 7 | 2 | 3 | 14 | 0 | 7 | 2 | 7 | 2 | 9
INPUTP | 1 | 54
IMPORTS | 2 | 2 | 7 | 2 | 9
@ -643,7 +646,7 @@ EQ | 82 |
# fsb/BERR0r & nDTACK_FSB
# fsb/BERR1r & nDTACK_FSB
# nAS_FSB & !fsb/ASrf
# nDTACK_FSB & !$OpTx$FX_DC$608
# nDTACK_FSB & !$OpTx$FX_DC$610
;Imported pterms FB3_8
# A_FSB<23> & !fsb/Ready1r & !iobs/IOReady &
nDTACK_FSB
@ -714,18 +717,18 @@ EQ | 82 |
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !fsb/BERR0r & !fsb/BERR1r &
fsb/Ready1r & $OpTx$FX_DC$608
fsb/Ready1r & $OpTx$FX_DC$610
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !fsb/BERR0r & !fsb/BERR1r &
iobs/IOReady & $OpTx$FX_DC$608;
iobs/IOReady & $OpTx$FX_DC$610;
nDTACK_FSB.CLK = CLK_FSB; // GCK
GLOBALS | 1 | 2 | CLK_FSB
MACROCELL | 7 | 0 | ram/RASEL
ATTRIBUTES | 8553216 | 0
OUTPUTMC | 10 | 6 | 5 | 6 | 1 | 4 | 13 | 4 | 10 | 4 | 4 | 4 | 9 | 4 | 14 | 6 | 4 | 6 | 7 | 6 | 10
OUTPUTMC | 12 | 6 | 5 | 6 | 1 | 4 | 13 | 4 | 10 | 4 | 4 | 4 | 9 | 4 | 14 | 6 | 4 | 6 | 7 | 6 | 10 | 6 | 6 | 6 | 8
INPUTS | 13 | ram/RS_FSM_FFd2 | ram/RS_FSM_FFd3 | ram/RS_FSM_FFd1 | A_FSB<23> | cnt/RefDone | nAS_FSB | ram/BACTr | fsb/ASrf | cnt/RefCnt<5> | cnt/RefCnt<6> | cnt/RefCnt<7> | A_FSB_19_IBUF$BUF0.EXP | EXP39_.EXP
INPUTMC | 11 | 6 | 15 | 6 | 13 | 7 | 3 | 6 | 2 | 3 | 0 | 0 | 7 | 0 | 10 | 0 | 9 | 0 | 8 | 7 | 1 | 7 | 17
INPUTP | 2 | 36 | 54
@ -1698,12 +1701,22 @@ EQ | 2 |
MACROCELL | 6 | 7 | RA_8_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | A_FSB<18> | ram/RASEL | A_FSB<9>
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 24 | 12
EQ | 2 |
RA<8> = A_FSB<9> & ram/RASEL
# A_FSB<18> & !ram/RASEL;
INPUTS | 8 | A_FSB<23> | A_FSB<18> | ram/RASEL | A_FSB<22> | A_FSB<21> | cs/nOverlay1 | cs/nOverlay0.EXP | A_FSB_21_IBUF$BUF0.EXP
INPUTMC | 4 | 7 | 0 | 3 | 13 | 6 | 6 | 6 | 8
INPUTP | 4 | 36 | 24 | 30 | 29
IMPORTS | 2 | 6 | 6 | 6 | 8
EQ | 11 |
RA<8> = A_FSB<23> & A_FSB<18>
# A_FSB<18> & !ram/RASEL
# A_FSB<22> & !A_FSB<21> & A_FSB<18>
# A_FSB<22> & A_FSB<18> & cs/nOverlay1
# !A_FSB<22> & A_FSB<18> & !cs/nOverlay1
;Imported pterms FB7_7
# A_FSB<9> & !A_FSB<23> & !A_FSB<22> & cs/nOverlay1 &
ram/RASEL
;Imported pterms FB7_9
# A_FSB<9> & !A_FSB<23> & A_FSB<22> & A_FSB<21> &
!cs/nOverlay1 & ram/RASEL;
MACROCELL | 6 | 10 | RA_9_OBUF
ATTRIBUTES | 264962 | 0
@ -1940,10 +1953,15 @@ EQ | 14 |
MACROCELL | 6 | 8 | A_FSB_21_IBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 1 | A_FSB<21>
INPUTP | 1 | 29
EQ | 1 |
OUTPUTMC | 1 | 6 | 7
INPUTS | 6 | A_FSB<21> | A_FSB<9> | A_FSB<23> | A_FSB<22> | cs/nOverlay1 | ram/RASEL
INPUTMC | 2 | 3 | 13 | 7 | 0
INPUTP | 4 | 29 | 12 | 36 | 30
EXPORTS | 1 | 6 | 7
EQ | 3 |
RA<10> = A_FSB<21>;
A_FSB_21_IBUF$BUF0.EXP = A_FSB<9> & !A_FSB<23> & A_FSB<22> & A_FSB<21> &
!cs/nOverlay1 & ram/RASEL
MACROCELL | 5 | 13 | nADoutLE1_OBUF
ATTRIBUTES | 8815366 | 0
@ -2010,75 +2028,75 @@ INPUTS | 0
EQ | 1 |
nAoutOE = Gnd;
MACROCELL | 0 | 17 | $OpTx$FX_DC$607
MACROCELL | 0 | 17 | $OpTx$FX_DC$609
ATTRIBUTES | 133888 | 0
OUTPUTMC | 5 | 2 | 1 | 2 | 0 | 2 | 2 | 2 | 3 | 2 | 17
INPUTS | 2 | nAS_FSB | fsb/ASrf
INPUTMC | 1 | 0 | 7
INPUTP | 1 | 54
EQ | 1 |
$OpTx$FX_DC$607 = nAS_FSB & !fsb/ASrf;
$OpTx$FX_DC$609 = nAS_FSB & !fsb/ASrf;
MACROCELL | 3 | 14 | $OpTx$FX_DC$608
MACROCELL | 3 | 14 | $OpTx$FX_DC$610
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 2 | 8 | 2 | 10
INPUTS | 5 | TimeoutB | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20>
INPUTMC | 1 | 6 | 0
INPUTP | 4 | 36 | 30 | 29 | 28
EQ | 2 |
$OpTx$FX_DC$608 = !TimeoutB
$OpTx$FX_DC$610 = !TimeoutB
# !A_FSB<23> & A_FSB<22> & !A_FSB<21> & A_FSB<20>;
MACROCELL | 2 | 0 | EXP14_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 1
INPUTS | 13 | A_FSB<22> | TimeoutB | fsb/VPA | $OpTx$FX_DC$607 | A_FSB<21> | A_FSB<23> | fsb/Ready1r | iobs/IOReady | cs/nOverlay1 | fsb/Ready0r | ram/RAMReady | A_FSB<20> | EXP25_.EXP
INPUTS | 13 | A_FSB<22> | TimeoutB | fsb/VPA | $OpTx$FX_DC$609 | A_FSB<21> | A_FSB<23> | fsb/Ready1r | iobs/IOReady | cs/nOverlay1 | fsb/Ready0r | ram/RAMReady | A_FSB<20> | EXP25_.EXP
INPUTMC | 9 | 6 | 0 | 2 | 1 | 0 | 17 | 2 | 4 | 3 | 17 | 3 | 13 | 6 | 3 | 6 | 17 | 2 | 17
INPUTP | 4 | 30 | 29 | 36 | 28
EXPORTS | 1 | 2 | 1
IMPORTS | 1 | 2 | 17
EQ | 36 |
EXP14_.EXP = !A_FSB<22> & TimeoutB & fsb/VPA &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# A_FSB<21> & TimeoutB & fsb/VPA &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# A_FSB<23> & !fsb/Ready1r & fsb/VPA &
!iobs/IOReady & !$OpTx$FX_DC$607
!iobs/IOReady & !$OpTx$FX_DC$609
# !A_FSB<23> & !A_FSB<22> & cs/nOverlay1 &
!fsb/Ready0r & fsb/VPA & !ram/RAMReady & !$OpTx$FX_DC$607
!fsb/Ready0r & fsb/VPA & !ram/RAMReady & !$OpTx$FX_DC$609
# A_FSB<22> & !A_FSB<21> & A_FSB<20> & !fsb/Ready1r &
fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$607
fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$609
;Imported pterms FB3_18
# A_FSB<9> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
MACROCELL | 2 | 2 | EXP15_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 1
INPUTS | 20 | A_FSB<23> | A_FSB<22> | A_FSB<21> | cs/nOverlay1 | fsb/Ready0r | fsb/VPA | ram/RAMReady | $OpTx$FX_DC$607 | A_FSB<14> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | nWE_FSB | fsb/Ready1r | iobs/IOReady | A_FSB<13> | nADoutLE1 | EXP16_.EXP
INPUTS | 20 | A_FSB<23> | A_FSB<22> | A_FSB<21> | cs/nOverlay1 | fsb/Ready0r | fsb/VPA | ram/RAMReady | $OpTx$FX_DC$609 | A_FSB<14> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | nWE_FSB | fsb/Ready1r | iobs/IOReady | A_FSB<13> | nADoutLE1 | EXP16_.EXP
INPUTMC | 9 | 3 | 13 | 6 | 3 | 2 | 1 | 6 | 17 | 0 | 17 | 2 | 4 | 3 | 17 | 5 | 13 | 2 | 3
INPUTP | 11 | 36 | 30 | 29 | 19 | 28 | 26 | 24 | 23 | 22 | 47 | 18
EXPORTS | 1 | 2 | 1
@ -2086,52 +2104,52 @@ IMPORTS | 1 | 2 | 3
EQ | 43 |
EXP15_.EXP = !A_FSB<23> & A_FSB<22> & A_FSB<21> &
!cs/nOverlay1 & !fsb/Ready0r & fsb/VPA & !ram/RAMReady &
!$OpTx$FX_DC$607
!$OpTx$FX_DC$609
# A_FSB<14> & A_FSB<22> & A_FSB<20> & A_FSB<19> &
A_FSB<18> & A_FSB<17> & A_FSB<16> & !cs/nOverlay1 & !nWE_FSB &
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$607
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$609
# A_FSB<13> & A_FSB<22> & A_FSB<20> & A_FSB<19> &
A_FSB<18> & A_FSB<17> & A_FSB<16> & !cs/nOverlay1 & !nWE_FSB &
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$607
!fsb/Ready1r & fsb/VPA & !iobs/IOReady & !$OpTx$FX_DC$609
# A_FSB<14> & !A_FSB<22> & A_FSB<21> & A_FSB<20> &
A_FSB<19> & A_FSB<18> & A_FSB<17> & A_FSB<16> &
cs/nOverlay1 & !nWE_FSB & !fsb/Ready1r & fsb/VPA & !iobs/IOReady &
!nADoutLE1 & !$OpTx$FX_DC$607
!nADoutLE1 & !$OpTx$FX_DC$609
# A_FSB<13> & !A_FSB<22> & A_FSB<21> & A_FSB<20> &
A_FSB<19> & A_FSB<18> & A_FSB<17> & A_FSB<16> &
cs/nOverlay1 & !nWE_FSB & !fsb/Ready1r & fsb/VPA & !iobs/IOReady &
!nADoutLE1 & !$OpTx$FX_DC$607
!nADoutLE1 & !$OpTx$FX_DC$609
;Imported pterms FB3_4
# A_FSB<9> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !TimeoutB & !fsb/BERR0r &
!fsb/BERR1r & fsb/Ready1r & !$OpTx$FX_DC$607
!fsb/BERR1r & fsb/Ready1r & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !TimeoutB & !fsb/BERR0r &
!fsb/BERR1r & iobs/IOReady & !$OpTx$FX_DC$607
!fsb/BERR1r & iobs/IOReady & !$OpTx$FX_DC$609
MACROCELL | 2 | 3 | EXP16_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 2
INPUTS | 28 | A_FSB<9> | A_FSB<15> | A_FSB<14> | A_FSB<13> | A_FSB<12> | A_FSB<11> | A_FSB<10> | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | cs/nOverlay1 | nWE_FSB | TimeoutA | fsb/Ready2r | fsb/VPA | $OpTx$FX_DC$607 | A_FSB<8> | BERR_IOBS | TimeoutB | fsb/BERR0r | fsb/BERR1r | fsb/Ready1r | iobs/IOReady
INPUTS | 28 | A_FSB<9> | A_FSB<15> | A_FSB<14> | A_FSB<13> | A_FSB<12> | A_FSB<11> | A_FSB<10> | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | cs/nOverlay1 | nWE_FSB | TimeoutA | fsb/Ready2r | fsb/VPA | $OpTx$FX_DC$609 | A_FSB<8> | BERR_IOBS | TimeoutB | fsb/BERR0r | fsb/BERR1r | fsb/Ready1r | iobs/IOReady
INPUTMC | 11 | 3 | 13 | 6 | 11 | 2 | 14 | 2 | 1 | 0 | 17 | 4 | 15 | 6 | 0 | 7 | 2 | 3 | 12 | 2 | 4 | 3 | 17
INPUTP | 17 | 12 | 21 | 19 | 18 | 17 | 15 | 13 | 36 | 30 | 29 | 28 | 26 | 24 | 23 | 22 | 47 | 11
EXPORTS | 1 | 2 | 2
@ -2140,27 +2158,27 @@ EQ | 25 |
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !TimeoutB & !fsb/BERR0r &
!fsb/BERR1r & fsb/Ready1r & !$OpTx$FX_DC$607
!fsb/BERR1r & fsb/Ready1r & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !TimeoutB & !fsb/BERR0r &
!fsb/BERR1r & iobs/IOReady & !$OpTx$FX_DC$607
!fsb/BERR1r & iobs/IOReady & !$OpTx$FX_DC$609
MACROCELL | 2 | 5 | EXP17_
ATTRIBUTES | 2048 | 0
@ -2290,17 +2308,17 @@ EQ | 47 |
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !fsb/BERR0r & !fsb/BERR1r &
fsb/Ready1r & $OpTx$FX_DC$608
fsb/Ready1r & $OpTx$FX_DC$610
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !fsb/BERR0r & !fsb/BERR1r &
iobs/IOReady & $OpTx$FX_DC$608
iobs/IOReady & $OpTx$FX_DC$610
MACROCELL | 2 | 10 | EXP21_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 9
INPUTS | 27 | A_FSB<9> | A_FSB<15> | A_FSB<14> | A_FSB<13> | A_FSB<12> | A_FSB<11> | A_FSB<10> | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | cs/nOverlay1 | nWE_FSB | TimeoutA | fsb/Ready2r | nDTACK_FSB | A_FSB<8> | BERR_IOBS | fsb/BERR0r | fsb/BERR1r | fsb/Ready1r | $OpTx$FX_DC$608 | iobs/IOReady
INPUTS | 27 | A_FSB<9> | A_FSB<15> | A_FSB<14> | A_FSB<13> | A_FSB<12> | A_FSB<11> | A_FSB<10> | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | cs/nOverlay1 | nWE_FSB | TimeoutA | fsb/Ready2r | nDTACK_FSB | A_FSB<8> | BERR_IOBS | fsb/BERR0r | fsb/BERR1r | fsb/Ready1r | $OpTx$FX_DC$610 | iobs/IOReady
INPUTMC | 10 | 3 | 13 | 6 | 11 | 2 | 14 | 2 | 8 | 4 | 15 | 7 | 2 | 3 | 12 | 2 | 4 | 3 | 14 | 3 | 17
INPUTP | 17 | 12 | 21 | 19 | 18 | 17 | 15 | 13 | 36 | 30 | 29 | 28 | 26 | 24 | 23 | 22 | 47 | 11
EXPORTS | 1 | 2 | 9
@ -2324,12 +2342,12 @@ EQ | 25 |
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !fsb/BERR0r & !fsb/BERR1r &
fsb/Ready1r & $OpTx$FX_DC$608
fsb/Ready1r & $OpTx$FX_DC$610
# A_FSB<9> & A_FSB<8> & A_FSB<15> & A_FSB<14> &
A_FSB<13> & A_FSB<12> & A_FSB<11> & A_FSB<10> & A_FSB<23> &
A_FSB<22> & A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> &
A_FSB<17> & A_FSB<16> & !BERR_IOBS & !fsb/BERR0r & !fsb/BERR1r &
iobs/IOReady & $OpTx$FX_DC$608
iobs/IOReady & $OpTx$FX_DC$610
MACROCELL | 2 | 11 | EXP22_
ATTRIBUTES | 2048 | 0
@ -2392,7 +2410,7 @@ EQ | 17 |
MACROCELL | 2 | 17 | EXP25_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 0
INPUTS | 22 | A_FSB<9> | A_FSB<15> | A_FSB<14> | A_FSB<13> | A_FSB<12> | A_FSB<11> | A_FSB<10> | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | cs/nOverlay1 | nWE_FSB | TimeoutA | fsb/Ready2r | fsb/VPA | $OpTx$FX_DC$607 | A_FSB<8>
INPUTS | 22 | A_FSB<9> | A_FSB<15> | A_FSB<14> | A_FSB<13> | A_FSB<12> | A_FSB<11> | A_FSB<10> | A_FSB<23> | A_FSB<22> | A_FSB<21> | A_FSB<20> | A_FSB<19> | A_FSB<18> | A_FSB<17> | A_FSB<16> | cs/nOverlay1 | nWE_FSB | TimeoutA | fsb/Ready2r | fsb/VPA | $OpTx$FX_DC$609 | A_FSB<8>
INPUTMC | 5 | 3 | 13 | 6 | 11 | 2 | 14 | 2 | 1 | 0 | 17
INPUTP | 17 | 12 | 21 | 19 | 18 | 17 | 15 | 13 | 36 | 30 | 29 | 28 | 26 | 24 | 23 | 22 | 47 | 11
EXPORTS | 1 | 2 | 0
@ -2401,27 +2419,27 @@ EQ | 25 |
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<9> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & !cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & A_FSB<14> & A_FSB<13> &
A_FSB<12> & A_FSB<11> & A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
# A_FSB<8> & A_FSB<15> & !A_FSB<14> & A_FSB<13> &
!A_FSB<12> & !A_FSB<11> & !A_FSB<10> & !A_FSB<23> & !A_FSB<22> &
A_FSB<21> & A_FSB<20> & A_FSB<19> & A_FSB<18> & A_FSB<17> &
A_FSB<16> & cs/nOverlay1 & !nWE_FSB & !TimeoutA & !fsb/Ready2r &
fsb/VPA & !$OpTx$FX_DC$607
fsb/VPA & !$OpTx$FX_DC$609
MACROCELL | 4 | 0 | EXP26_
ATTRIBUTES | 2048 | 0
@ -2760,7 +2778,7 @@ EQ | 26 |
!ram/RS_FSM_FFd2 & !ram/RS_FSM_FFd1 & cnt/RefCnt<5> & cnt/RefCnt<6> &
cnt/RefCnt<7>
PIN | A_FSB<9> | 64 | 0 | N/A | 12 | 7 | 2 | 14 | 6 | 7 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 10 | 2 | 17
PIN | A_FSB<9> | 64 | 0 | N/A | 12 | 8 | 2 | 14 | 6 | 6 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 10 | 2 | 17 | 6 | 8
PIN | A_FSB<8> | 64 | 0 | N/A | 11 | 7 | 2 | 10 | 6 | 4 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 15 | 2 | 17
PIN | A_FSB<15> | 64 | 0 | N/A | 21 | 8 | 2 | 14 | 4 | 10 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 17
PIN | A_FSB<14> | 64 | 0 | N/A | 19 | 18 | 4 | 5 | 4 | 13 | 2 | 4 | 2 | 14 | 4 | 4 | 2 | 10 | 2 | 7 | 4 | 1 | 4 | 0 | 4 | 9 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 15 | 2 | 17 | 7 | 9
@ -2768,9 +2786,9 @@ PIN | A_FSB<13> | 64 | 0 | N/A | 18 | 17 | 4 | 5 | 4 | 13 | 2 | 4 | 2 | 14 | 4 |
PIN | A_FSB<12> | 64 | 0 | N/A | 17 | 8 | 2 | 14 | 4 | 13 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 17
PIN | A_FSB<11> | 64 | 0 | N/A | 15 | 8 | 2 | 14 | 6 | 1 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 17
PIN | A_FSB<10> | 64 | 0 | N/A | 13 | 8 | 2 | 14 | 6 | 5 | 2 | 6 | 2 | 3 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 17
PIN | A_FSB<23> | 64 | 0 | N/A | 36 | 51 | 7 | 6 | 4 | 7 | 4 | 17 | 6 | 6 | 7 | 2 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 1 | 2 | 12 | 7 | 11 | 2 | 7 | 7 | 0 | 6 | 14 | 7 | 3 | 6 | 13 | 4 | 3 | 7 | 8 | 4 | 12 | 7 | 14 | 6 | 17 | 7 | 10 | 3 | 5 | 7 | 4 | 4 | 1 | 3 | 14 | 2 | 0 | 2 | 2 | 2 | 3 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 11 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 2 | 4 | 4 | 4 | 5 | 4 | 6 | 4 | 8 | 4 | 11 | 4 | 13 | 4 | 16 | 6 | 0 | 6 | 16 | 7 | 7 | 7 | 9 | 7 | 15 | 7 | 16 | 7 | 17
PIN | A_FSB<22> | 64 | 0 | N/A | 30 | 47 | 7 | 6 | 4 | 7 | 4 | 16 | 6 | 6 | 7 | 2 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 0 | 2 | 11 | 7 | 11 | 2 | 7 | 6 | 16 | 6 | 14 | 7 | 3 | 6 | 11 | 4 | 2 | 7 | 7 | 4 | 11 | 7 | 13 | 6 | 17 | 7 | 10 | 3 | 5 | 7 | 4 | 4 | 1 | 3 | 14 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 0 | 4 | 4 | 4 | 5 | 4 | 6 | 4 | 13 | 6 | 13 | 7 | 1 | 7 | 9 | 7 | 12 | 7 | 15 | 7 | 16 | 7 | 17
PIN | A_FSB<21> | 64 | 0 | N/A | 29 | 46 | 7 | 6 | 4 | 6 | 4 | 16 | 6 | 6 | 7 | 2 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 0 | 2 | 12 | 7 | 11 | 2 | 7 | 6 | 16 | 6 | 13 | 7 | 3 | 6 | 11 | 4 | 2 | 7 | 7 | 4 | 11 | 7 | 13 | 6 | 17 | 7 | 10 | 3 | 5 | 7 | 4 | 6 | 8 | 4 | 1 | 3 | 14 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 11 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 0 | 4 | 4 | 4 | 5 | 4 | 8 | 4 | 13 | 7 | 9 | 7 | 12 | 7 | 16 | 7 | 17
PIN | A_FSB<23> | 64 | 0 | N/A | 36 | 53 | 7 | 6 | 4 | 7 | 4 | 17 | 6 | 6 | 7 | 2 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 1 | 2 | 12 | 7 | 11 | 2 | 7 | 7 | 0 | 6 | 14 | 7 | 3 | 6 | 13 | 4 | 3 | 7 | 8 | 4 | 12 | 7 | 14 | 6 | 17 | 6 | 7 | 7 | 10 | 3 | 5 | 7 | 4 | 4 | 1 | 3 | 14 | 2 | 0 | 2 | 2 | 2 | 3 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 11 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 2 | 4 | 4 | 4 | 5 | 4 | 6 | 4 | 8 | 4 | 11 | 4 | 13 | 4 | 16 | 6 | 0 | 6 | 8 | 6 | 16 | 7 | 7 | 7 | 9 | 7 | 15 | 7 | 16 | 7 | 17
PIN | A_FSB<22> | 64 | 0 | N/A | 30 | 49 | 7 | 6 | 4 | 7 | 4 | 16 | 6 | 6 | 7 | 2 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 0 | 2 | 11 | 7 | 11 | 2 | 7 | 6 | 16 | 6 | 14 | 7 | 3 | 6 | 11 | 4 | 2 | 7 | 7 | 4 | 11 | 7 | 13 | 6 | 17 | 6 | 7 | 7 | 10 | 3 | 5 | 7 | 4 | 4 | 1 | 3 | 14 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 0 | 4 | 4 | 4 | 5 | 4 | 6 | 4 | 13 | 6 | 8 | 6 | 13 | 7 | 1 | 7 | 9 | 7 | 12 | 7 | 15 | 7 | 16 | 7 | 17
PIN | A_FSB<21> | 64 | 0 | N/A | 29 | 47 | 7 | 6 | 4 | 6 | 4 | 16 | 6 | 6 | 7 | 2 | 6 | 3 | 2 | 4 | 2 | 14 | 2 | 0 | 2 | 12 | 7 | 11 | 2 | 7 | 6 | 16 | 6 | 13 | 7 | 3 | 6 | 11 | 4 | 2 | 7 | 7 | 4 | 11 | 7 | 13 | 6 | 17 | 6 | 7 | 7 | 10 | 3 | 5 | 7 | 4 | 6 | 8 | 4 | 1 | 3 | 14 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 11 | 2 | 13 | 2 | 15 | 2 | 17 | 4 | 0 | 4 | 4 | 4 | 5 | 4 | 8 | 4 | 13 | 7 | 9 | 7 | 12 | 7 | 16 | 7 | 17
PIN | A_FSB<20> | 64 | 0 | N/A | 28 | 27 | 4 | 7 | 4 | 16 | 6 | 6 | 7 | 2 | 2 | 4 | 2 | 14 | 2 | 1 | 2 | 12 | 2 | 7 | 4 | 3 | 7 | 8 | 4 | 12 | 6 | 10 | 7 | 10 | 3 | 5 | 4 | 1 | 3 | 14 | 2 | 0 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 17 | 4 | 0
PIN | A_FSB<19> | 64 | 0 | N/A | 26 | 20 | 4 | 1 | 4 | 8 | 2 | 4 | 2 | 14 | 4 | 0 | 2 | 10 | 2 | 7 | 4 | 2 | 7 | 7 | 4 | 11 | 6 | 10 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 13 | 2 | 15 | 2 | 17 | 7 | 2
PIN | A_FSB<18> | 64 | 0 | N/A | 24 | 19 | 4 | 4 | 4 | 13 | 2 | 4 | 2 | 14 | 6 | 7 | 2 | 10 | 2 | 7 | 4 | 1 | 4 | 0 | 4 | 8 | 2 | 2 | 2 | 3 | 2 | 5 | 2 | 6 | 2 | 9 | 2 | 13 | 2 | 15 | 2 | 17 | 7 | 9

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cpld/XC95144XL/MXSE.pad
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
2- 7-2022 4:04AM
2-14-2022 7:35PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'

81
cpld/XC95144XL/MXSE.rpt
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@ -1,7 +1,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: MXSE Date: 2- 7-2022, 4:04AM
Design Name: MXSE Date: 2-14-2022, 7:35PM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
@ -9,7 +9,7 @@ Fitting Status: Successful
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
105/144 ( 73%) 429 /720 ( 60%) 227/432 ( 53%) 80 /144 ( 56%) 67 /81 ( 83%)
105/144 ( 73%) 434 /720 ( 60%) 227/432 ( 53%) 80 /144 ( 56%) 67 /81 ( 83%)
** Function Block Resources **
@ -21,10 +21,10 @@ FB3 6/18 39/54 81/90 10/10*
FB4 18/18* 29/54 34/90 9/10
FB5 13/18 31/54 81/90 8/10
FB6 18/18* 34/54 62/90 10/10*
FB7 15/18 39/54 68/90 6/10
FB7 15/18 39/54 73/90 6/10
FB8 12/18 36/54 81/90 5/10
----- ----- ----- -----
105/144 227/432 429/720 67/81
105/144 227/432 434/720 67/81
* - Resource is exhausted
@ -103,7 +103,7 @@ nDinLE 2 3 FB6_17 86 I/O O STD FAST RESET
RA<1> 2 3 FB7_2 50 I/O O STD FAST
RA<7> 2 3 FB7_5 52 I/O O STD FAST
RA<0> 2 3 FB7_6 53 I/O O STD FAST
RA<8> 2 3 FB7_8 54 I/O O STD FAST
RA<8> 7 7 FB7_8 54 I/O O STD FAST
RA<10> 1 1 FB7_9 55 I/O O STD FAST
RA<9> 2 3 FB7_11 56 I/O O STD FAST
RA<11> 1 1 FB8_2 63 I/O O STD FAST
@ -133,7 +133,7 @@ cnt/RefCnt<2> 1 2 FB1_14 STD RESET
cnt/RefCnt<1> 1 1 FB1_15 STD RESET
cnt/RefCnt<0> 0 0 FB1_16 STD RESET
RefAck 1 2 FB1_17 STD RESET
$OpTx$FX_DC$607 1 2 FB1_18 STD
$OpTx$FX_DC$609 1 2 FB1_18 STD
iobm/VPArr 1 1 FB2_14 STD RESET
iobm/VPArf 1 1 FB2_15 STD RESET
iobm/RESrr 1 1 FB2_16 STD RESET
@ -153,7 +153,7 @@ iobm/IOS_FSM_FFd2 2 4 FB4_10 STD RESET
iobm/IOS_FSM_FFd1 2 4 FB4_12 STD RESET
fsb/BERR1r 2 4 FB4_13 STD RESET
cs/nOverlay1 2 3 FB4_14 STD RESET
$OpTx$FX_DC$608 2 5 FB4_15 STD
$OpTx$FX_DC$610 2 5 FB4_15 STD
IOU0 3 5 FB4_16 STD RESET
IOL0 3 5 FB4_17 STD RESET
@ -270,7 +270,7 @@ cnt/RefCnt<2> 1 0 0 4 FB1_14 19 I/O I
cnt/RefCnt<1> 1 0 0 4 FB1_15 20 I/O I
cnt/RefCnt<0> 0 0 0 5 FB1_16 (b) (b)
RefAck 1 0 0 4 FB1_17 22 GCK/I/O GCK
$OpTx$FX_DC$607 1 0 0 4 FB1_18 (b) (b)
$OpTx$FX_DC$609 1 0 0 4 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: IOACT 7: cnt/RefCnt<4> 12: nAS_FSB
@ -299,7 +299,7 @@ cnt/RefCnt<2> ..XX.................................... 2
cnt/RefCnt<1> ..X..................................... 1
cnt/RefCnt<0> ........................................ 0
RefAck ..............XX........................ 2
$OpTx$FX_DC$607 .........X.X............................ 2
$OpTx$FX_DC$609 .........X.X............................ 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
@ -363,8 +363,8 @@ nROMWE 1 0 0 4 FB3_17 34 I/O O
(unused) 0 0 \/5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$607 14: A_FSB<21> 27: fsb/Ready1r
2: $OpTx$FX_DC$608 15: A_FSB<22> 28: fsb/Ready2r
1: $OpTx$FX_DC$609 14: A_FSB<21> 27: fsb/Ready1r
2: $OpTx$FX_DC$610 15: A_FSB<22> 28: fsb/Ready2r
3: A_FSB<10> 16: A_FSB<23> 29: fsb/VPA
4: A_FSB<11> 17: A_FSB<8> 30: iobs/IORW1
5: A_FSB<12> 18: A_FSB<9> 31: iobs/IOReady
@ -406,7 +406,7 @@ nVPA_FSB 1 0 0 4 FB4_11 93 I/O O
iobm/IOS_FSM_FFd1 2 0 0 3 FB4_12 94 I/O I
fsb/BERR1r 2 0 0 3 FB4_13 (b) (b)
cs/nOverlay1 2 0 0 3 FB4_14 95 I/O I
$OpTx$FX_DC$608 2 0 0 3 FB4_15 96 I/O I
$OpTx$FX_DC$610 2 0 0 3 FB4_15 96 I/O I
IOU0 3 0 0 2 FB4_16 (b) (b)
IOL0 3 0 0 2 FB4_17 97 I/O I
iobs/IOReady 4 0 0 1 FB4_18 (b) (b)
@ -439,7 +439,7 @@ nVPA_FSB ...........X.............X.............. 2
iobm/IOS_FSM_FFd1 ............XXXX........................ 4
fsb/BERR1r ....X....XX..............X.............. 4
cs/nOverlay1 ........XX...............X.............. 3
$OpTx$FX_DC$608 XXXX...X................................ 5
$OpTx$FX_DC$610 XXXX...X................................ 5
IOU0 ...................X..XXX..X............ 5
IOL0 .................X....XXX.X............. 5
iobs/IOReady .....X...X......X.X..X.XXX.............. 8
@ -570,9 +570,9 @@ cnt/RefDone 2 0 0 3 FB7_3 (b) (b)
fsb/Ready0r 3 0 0 2 FB7_4 (b) (b)
RA<7> 2 0 0 3 FB7_5 52 I/O O
RA<0> 2 0 0 3 FB7_6 53 I/O O
cs/nOverlay0 3 0 0 2 FB7_7 (b) (b)
RA<8> 2 0 0 3 FB7_8 54 I/O O
RA<10> 1 0 0 4 FB7_9 55 I/O O
cs/nOverlay0 3 0 \/1 1 FB7_7 (b) (b)
RA<8> 7 2<- 0 0 FB7_8 54 I/O O
RA<10> 1 0 /\1 3 FB7_9 55 I/O O
cnt/TimeoutBPre 3 0 0 2 FB7_10 (b) (b)
RA<9> 2 0 \/3 0 FB7_11 56 I/O O
TimeoutA 3 3<- \/5 0 FB7_12 58 I/O (b)
@ -607,7 +607,7 @@ fsb/Ready0r .......XXX.................XXXX...X..... 8
RA<7> ..X........X.......................X.... 3
RA<0> X....X.............................X.... 3
cs/nOverlay0 ......XXXX................X.X.XX........ 8
RA<8> ...X........X......................X.... 3
RA<8> ...X...XXX..X..............X.......X.... 7
RA<10> .......X................................ 1
cnt/TimeoutBPre ................XXXXXXXX.X..X.X......... 11
RA<9> ....X.X............................X.... 3
@ -676,10 +676,10 @@ ram/RAMDIS1 .......XXX...XXXXXX......X...XX..XXX.... 15
********** Mapped Logic **********
$OpTx$FX_DC$607 <= (nAS_FSB AND NOT fsb/ASrf);
$OpTx$FX_DC$609 <= (nAS_FSB AND NOT fsb/ASrf);
$OpTx$FX_DC$608 <= ((NOT TimeoutB)
$OpTx$FX_DC$610 <= ((NOT TimeoutB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20)));
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
@ -907,8 +907,15 @@ RA(7) <= ((A_FSB(8) AND ram/RASEL)
OR (A_FSB(17) AND NOT ram/RASEL));
RA(8) <= ((A_FSB(9) AND ram/RASEL)
OR (A_FSB(18) AND NOT ram/RASEL));
RA(8) <= ((A_FSB(9) AND NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
ram/RASEL)
OR (A_FSB(9) AND NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND ram/RASEL)
OR (A_FSB(23) AND A_FSB(18))
OR (A_FSB(18) AND NOT ram/RASEL)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(18))
OR (A_FSB(22) AND A_FSB(18) AND cs/nOverlay1)
OR (NOT A_FSB(22) AND A_FSB(18) AND NOT cs/nOverlay1));
RA(9) <= ((A_FSB(20) AND ram/RASEL)
@ -1068,40 +1075,40 @@ fsb/Ready2r_D <= ((nAS_FSB AND NOT fsb/ASrf)
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
fsb/VPA_D <= ((EXP25_.EXP)
OR (NOT A_FSB(22) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (A_FSB(21) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND NOT $OpTx$FX_DC$607)
NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND NOT $OpTx$FX_DC$609)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (EXP16_.EXP)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
NOT nADoutLE1 AND NOT $OpTx$FX_DC$607)
NOT nADoutLE1 AND NOT $OpTx$FX_DC$609)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
NOT nADoutLE1 AND NOT $OpTx$FX_DC$607)
OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$607)
OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$607)
OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$607)
NOT nADoutLE1 AND NOT $OpTx$FX_DC$609)
OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$609)
OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$609)
OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$609)
OR (A_FSB(23) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (NOT A_FSB(20) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607));
NOT $OpTx$FX_DC$609));
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
@ -1364,7 +1371,7 @@ nDTACK_FSB_D <= ((EXP18_.EXP)
OR (fsb/BERR0r AND nDTACK_FSB)
OR (fsb/BERR1r AND nDTACK_FSB)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (nDTACK_FSB AND NOT $OpTx$FX_DC$608));
OR (nDTACK_FSB AND NOT $OpTx$FX_DC$610));
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
nDinLE_D <= ((iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd1)

20
cpld/XC95144XL/MXSE.syr
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@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.84 secs
Total CPU time to Xst completion: 0.87 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.86 secs
Total CPU time to Xst completion: 0.89 secs
--> Reading design: MXSE.prj
@ -433,16 +433,16 @@ Design Statistics
# IOs : 67
Cell Usage :
# BELS : 605
# AND2 : 170
# AND3 : 24
# BELS : 607
# AND2 : 169
# AND3 : 25
# AND4 : 14
# AND6 : 2
# AND7 : 1
# AND8 : 3
# GND : 6
# INV : 255
# OR2 : 107
# INV : 256
# OR2 : 108
# OR3 : 9
# OR4 : 1
# VCC : 1
@ -456,12 +456,12 @@ Cell Usage :
=========================================================================
Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 28.61 secs
Total REAL time to Xst completion: 27.00 secs
Total CPU time to Xst completion: 27.11 secs
-->
Total memory usage is 203796 kilobytes
Total memory usage is 204052 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)

356
cpld/XC95144XL/MXSE.tspec
View File

@ -1,81 +1,81 @@
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd4.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:iobm/IOS_FSM_FFd4.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:iobm/IOS_FSM_FFd4.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:iobm/IOS_FSM_FFd4.D:666
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:iobm/IOS_FSM_FFd4.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:iobm/IOS_FSM_FFd4.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:iobm/IOS_FSM_FFd3.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:IOBERR.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:IOACT.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:IOBERR.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:IOBERR.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:IOBERR.D:666
TS_CLK_FSB:FROM:cs/nOverlay0.Q:TO:cs/nOverlay1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:cs/nOverlay1.CE:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/Once.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:RefAck.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:cnt/RefDone.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/Once.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:BERR_IOBS.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:iobs/IORW1.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:IORW0.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:iobs/IORW1.Q:TO:IORW0.D:400
TS_CLK_FSB:FROM:cs/nOverlay0.Q:TO:cs/nOverlay0.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:cs/nOverlay0.D:400
TS_CLK_FSB:FROM:cs/nOverlay0.Q:TO:cs/nOverlay0.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IOL0.D:400
TS_CLK_FSB:FROM:iobs/IOL1.Q:TO:IOL0.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IOL0.CE:400
@ -85,35 +85,35 @@ TS_CLK_FSB:FROM:iobs/IOU1.Q:TO:IOU0.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IOU0.CE:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IOU0.CE:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:TimeoutA.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:TimeoutB.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/TimeoutBPre.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:cnt/TimeoutBPre.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:TimeoutB.Q:TO:TimeoutB.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/TimeoutBPre.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:cnt/TimeoutBPre.Q:TO:cnt/TimeoutBPre.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/BERR0r.D:400
TS_CLK_FSB:FROM:TimeoutB.Q:TO:fsb/BERR0r.D:400
TS_CLK_FSB:FROM:fsb/BERR0r.Q:TO:fsb/BERR0r.D:400
@ -121,263 +121,275 @@ TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/BERR1r.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:fsb/BERR1r.D:400
TS_CLK_FSB:FROM:fsb/BERR1r.Q:TO:fsb/BERR1r.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/Ready0r.D:400
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:fsb/Ready0r.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready0r.D:400
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:fsb/Ready0r.D:400
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:fsb/Ready0r.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:fsb/Ready1r.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/Ready2r.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready2r.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:fsb/Ready2r.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready2r.D:400
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:fsb/Ready2r.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/VPA.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:TimeoutB.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/BERR0r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/BERR1r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:TimeoutB.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:fsb/VPA.Q:TO:fsb/VPA.D:400
TS_CLK_FSB:FROM:iobs/Load1.Q:TO:iobs/IOL1.CE:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/IORW1.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:iobs/IORW1.Q:TO:iobs/IORW1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:iobs/IOReady.D:400
TS_CLK_FSB:FROM:iobs/Load1.Q:TO:iobs/IOU1.CE:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RAMDIS2.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:nDTACK_FSB_OBUF.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:ram/RAMDIS2.Q:TO:ram/RAMDIS2.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/BERR0r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/BERR1r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:TimeoutB.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:TimeoutA.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:nDTACK_FSB_OBUF.Q:TO:nDTACK_FSB_OBUF.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RASEL.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd3.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/PS_FSM_FFd2.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/PS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/PS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/PS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/PS_FSM_FFd1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<0>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<5>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<6>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<1>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<1>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<2>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<2>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<2>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<3>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<3>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<3>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<3>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<3>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<4>.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Load1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/BACTr.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:RefAck.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<7>.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:RefAck.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:ALE0S.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:RefAck.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:ALE0S.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:ALE0S.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/Once.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IOREQ.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/Clear1.D:400
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/Clear1.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Clear1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RAMDIS1.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMReady.D:400
TS_CLK_FSB:FROM:ram/RASEL.Q:TO:nCAS_OBUF.D:400
TS_CLK_FSB:FROM:iobs/Load1.Q:TO:nADoutLE1_OBUF.D:400
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:nADoutLE1_OBUF.D:400
TS_CLK_FSB:FROM:iobs/Load1.Q:TO:nADoutLE1_OBUF.D:400
TS_CLK_FSB:FROM:iobs/Clear1.Q:TO:nADoutLE1_OBUF.D:400
TS_CLK2X_IOB:FROM:nVMA_IOB_OBUF.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:IOACT.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/VPArr.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/VPArf.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:IOACT.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/VPArf.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/VPArr.Q:TO:nVMA_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd2.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:iobm/IOS_FSM_FFd2.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:iobm/IOS_FSM_FFd2.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd2.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:iobm/IOS_FSM_FFd2.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd1.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:iobm/IOS_FSM_FFd1.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:iobm/IOS_FSM_FFd1.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:iobm/IOS_FSM_FFd1.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:iobm/IOS_FSM_FFd1.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd1.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<0>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<1>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<2>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<3>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:nVMA_IOB_OBUF.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<4>.D:666
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:nVMA_IOB_OBUF.Q:TO:iobm/ETACK.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:ALE0M.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:ALE0M.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:ALE0M.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:ALE0M.D:666
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:ALE0M.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:ALE0M.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nAS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nAS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nAS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:nAS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nDinLE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nDinLE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nAS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:nDinLE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nDoutOE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nDinLE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nDinLE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nDoutOE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nDoutOE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nDoutOE_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nLDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nLDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nLDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:nLDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nUDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nUDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nLDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nLDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nUDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:nUDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nUDS_IOB_OBUF.D:666
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nUDS_IOB_OBUF.D:666

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@ -3,7 +3,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: MXSE Date: 2- 7-2022, 4:04AM
Design Name: MXSE Date: 2-14-2022, 7:35PM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
@ -11,7 +11,7 @@ Fitting Status: Successful
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
105/144 ( 73%) 429 /720 ( 60%) 227/432 ( 53%) 80 /144 ( 56%) 67 /81 ( 83%)
105/144 ( 73%) 434 /720 ( 60%) 227/432 ( 53%) 80 /144 ( 56%) 67 /81 ( 83%)
** Function Block Resources **
@ -23,10 +23,10 @@ FB3 6/18 39/54 81/90 10/10*
FB4 18/18* 29/54 34/90 9/10
FB5 13/18 31/54 81/90 8/10
FB6 18/18* 34/54 62/90 10/10*
FB7 15/18 39/54 68/90 6/10
FB7 15/18 39/54 73/90 6/10
FB8 12/18 36/54 81/90 5/10
----- ----- ----- -----
105/144 227/432 429/720 67/81
105/144 227/432 434/720 67/81
* - Resource is exhausted
@ -105,7 +105,7 @@ nDinLE 2 3 FB6_17 86 I/O O STD FAST RESET
RA<1> 2 3 FB7_2 50 I/O O STD FAST
RA<7> 2 3 FB7_5 52 I/O O STD FAST
RA<0> 2 3 FB7_6 53 I/O O STD FAST
RA<8> 2 3 FB7_8 54 I/O O STD FAST
RA<8> 7 7 FB7_8 54 I/O O STD FAST
RA<10> 1 1 FB7_9 55 I/O O STD FAST
RA<9> 2 3 FB7_11 56 I/O O STD FAST
RA<11> 1 1 FB8_2 63 I/O O STD FAST
@ -135,7 +135,7 @@ cnt/RefCnt<2> 1 2 FB1_14 STD RESET
cnt/RefCnt<1> 1 1 FB1_15 STD RESET
cnt/RefCnt<0> 0 0 FB1_16 STD RESET
RefAck 1 2 FB1_17 STD RESET
$OpTx$FX_DC$607 1 2 FB1_18 STD
$OpTx$FX_DC$609 1 2 FB1_18 STD
iobm/VPArr 1 1 FB2_14 STD RESET
iobm/VPArf 1 1 FB2_15 STD RESET
iobm/RESrr 1 1 FB2_16 STD RESET
@ -155,7 +155,7 @@ iobm/IOS_FSM_FFd2 2 4 FB4_10 STD RESET
iobm/IOS_FSM_FFd1 2 4 FB4_12 STD RESET
fsb/BERR1r 2 4 FB4_13 STD RESET
cs/nOverlay1 2 3 FB4_14 STD RESET
$OpTx$FX_DC$608 2 5 FB4_15 STD
$OpTx$FX_DC$610 2 5 FB4_15 STD
IOU0 3 5 FB4_16 STD RESET
IOL0 3 5 FB4_17 STD RESET
@ -272,7 +272,7 @@ cnt/RefCnt<2> 1 0 0 4 FB1_14 19 I/O I
cnt/RefCnt<1> 1 0 0 4 FB1_15 20 I/O I
cnt/RefCnt<0> 0 0 0 5 FB1_16 (b) (b)
RefAck 1 0 0 4 FB1_17 22 GCK/I/O GCK
$OpTx$FX_DC$607 1 0 0 4 FB1_18 (b) (b)
$OpTx$FX_DC$609 1 0 0 4 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: IOACT 7: cnt/RefCnt<4> 12: nAS_FSB
@ -301,7 +301,7 @@ cnt/RefCnt<2> ..XX.................................... 2
cnt/RefCnt<1> ..X..................................... 1
cnt/RefCnt<0> ........................................ 0
RefAck ..............XX........................ 2
$OpTx$FX_DC$607 .........X.X............................ 2
$OpTx$FX_DC$609 .........X.X............................ 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
@ -365,8 +365,8 @@ nROMWE 1 0 0 4 FB3_17 34 I/O O
(unused) 0 0 \/5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$607 14: A_FSB<21> 27: fsb/Ready1r
2: $OpTx$FX_DC$608 15: A_FSB<22> 28: fsb/Ready2r
1: $OpTx$FX_DC$609 14: A_FSB<21> 27: fsb/Ready1r
2: $OpTx$FX_DC$610 15: A_FSB<22> 28: fsb/Ready2r
3: A_FSB<10> 16: A_FSB<23> 29: fsb/VPA
4: A_FSB<11> 17: A_FSB<8> 30: iobs/IORW1
5: A_FSB<12> 18: A_FSB<9> 31: iobs/IOReady
@ -408,7 +408,7 @@ nVPA_FSB 1 0 0 4 FB4_11 93 I/O O
iobm/IOS_FSM_FFd1 2 0 0 3 FB4_12 94 I/O I
fsb/BERR1r 2 0 0 3 FB4_13 (b) (b)
cs/nOverlay1 2 0 0 3 FB4_14 95 I/O I
$OpTx$FX_DC$608 2 0 0 3 FB4_15 96 I/O I
$OpTx$FX_DC$610 2 0 0 3 FB4_15 96 I/O I
IOU0 3 0 0 2 FB4_16 (b) (b)
IOL0 3 0 0 2 FB4_17 97 I/O I
iobs/IOReady 4 0 0 1 FB4_18 (b) (b)
@ -441,7 +441,7 @@ nVPA_FSB ...........X.............X.............. 2
iobm/IOS_FSM_FFd1 ............XXXX........................ 4
fsb/BERR1r ....X....XX..............X.............. 4
cs/nOverlay1 ........XX...............X.............. 3
$OpTx$FX_DC$608 XXXX...X................................ 5
$OpTx$FX_DC$610 XXXX...X................................ 5
IOU0 ...................X..XXX..X............ 5
IOL0 .................X....XXX.X............. 5
iobs/IOReady .....X...X......X.X..X.XXX.............. 8
@ -572,9 +572,9 @@ cnt/RefDone 2 0 0 3 FB7_3 (b) (b)
fsb/Ready0r 3 0 0 2 FB7_4 (b) (b)
RA<7> 2 0 0 3 FB7_5 52 I/O O
RA<0> 2 0 0 3 FB7_6 53 I/O O
cs/nOverlay0 3 0 0 2 FB7_7 (b) (b)
RA<8> 2 0 0 3 FB7_8 54 I/O O
RA<10> 1 0 0 4 FB7_9 55 I/O O
cs/nOverlay0 3 0 \/1 1 FB7_7 (b) (b)
RA<8> 7 2<- 0 0 FB7_8 54 I/O O
RA<10> 1 0 /\1 3 FB7_9 55 I/O O
cnt/TimeoutBPre 3 0 0 2 FB7_10 (b) (b)
RA<9> 2 0 \/3 0 FB7_11 56 I/O O
TimeoutA 3 3<- \/5 0 FB7_12 58 I/O (b)
@ -609,7 +609,7 @@ fsb/Ready0r .......XXX.................XXXX...X..... 8
RA<7> ..X........X.......................X.... 3
RA<0> X....X.............................X.... 3
cs/nOverlay0 ......XXXX................X.X.XX........ 8
RA<8> ...X........X......................X.... 3
RA<8> ...X...XXX..X..............X.......X.... 7
RA<10> .......X................................ 1
cnt/TimeoutBPre ................XXXXXXXX.X..X.X......... 11
RA<9> ....X.X............................X.... 3
@ -678,10 +678,10 @@ ram/RAMDIS1 .......XXX...XXXXXX......X...XX..XXX.... 15
********** Mapped Logic **********
$OpTx$FX_DC$607 <= (nAS_FSB AND NOT fsb/ASrf);
$OpTx$FX_DC$609 <= (nAS_FSB AND NOT fsb/ASrf);
$OpTx$FX_DC$608 <= ((NOT TimeoutB)
$OpTx$FX_DC$610 <= ((NOT TimeoutB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20)));
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
@ -909,8 +909,15 @@ RA(7) <= ((A_FSB(8) AND ram/RASEL)
OR (A_FSB(17) AND NOT ram/RASEL));
RA(8) <= ((A_FSB(9) AND ram/RASEL)
OR (A_FSB(18) AND NOT ram/RASEL));
RA(8) <= ((A_FSB(9) AND NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
ram/RASEL)
OR (A_FSB(9) AND NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND ram/RASEL)
OR (A_FSB(23) AND A_FSB(18))
OR (A_FSB(18) AND NOT ram/RASEL)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(18))
OR (A_FSB(22) AND A_FSB(18) AND cs/nOverlay1)
OR (NOT A_FSB(22) AND A_FSB(18) AND NOT cs/nOverlay1));
RA(9) <= ((A_FSB(20) AND ram/RASEL)
@ -1070,40 +1077,40 @@ fsb/Ready2r_D <= ((nAS_FSB AND NOT fsb/ASrf)
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
fsb/VPA_D <= ((EXP25_.EXP)
OR (NOT A_FSB(22) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (A_FSB(21) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND NOT $OpTx$FX_DC$607)
NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND NOT $OpTx$FX_DC$609)
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (EXP16_.EXP)
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
NOT nADoutLE1 AND NOT $OpTx$FX_DC$607)
NOT nADoutLE1 AND NOT $OpTx$FX_DC$609)
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
NOT nADoutLE1 AND NOT $OpTx$FX_DC$607)
OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$607)
OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$607)
OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$607)
NOT nADoutLE1 AND NOT $OpTx$FX_DC$609)
OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$609)
OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$609)
OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$609)
OR (A_FSB(23) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607)
NOT $OpTx$FX_DC$609)
OR (NOT A_FSB(20) AND TimeoutB AND fsb/VPA AND
NOT $OpTx$FX_DC$607));
NOT $OpTx$FX_DC$609));
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
@ -1366,7 +1373,7 @@ nDTACK_FSB_D <= ((EXP18_.EXP)
OR (fsb/BERR0r AND nDTACK_FSB)
OR (fsb/BERR1r AND nDTACK_FSB)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (nDTACK_FSB AND NOT $OpTx$FX_DC$608));
OR (nDTACK_FSB AND NOT $OpTx$FX_DC$610));
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
nDinLE_D <= ((iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd1)

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@ -6,10 +6,10 @@
********** Mapped Logic **********
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$607 <= (nAS_FSB AND NOT fsb/ASrf);
$OpTx$FX_DC$609 <= (nAS_FSB AND NOT fsb/ASrf);
</td></tr><tr><td>
</td></tr><tr><td>
$OpTx$FX_DC$608 <= ((NOT TimeoutB)
$OpTx$FX_DC$610 <= ((NOT TimeoutB)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20)));
</td></tr><tr><td>
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
@ -237,8 +237,15 @@ RA(7) <= ((A_FSB(8) AND ram/RASEL)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(17) AND NOT ram/RASEL));
</td></tr><tr><td>
</td></tr><tr><td>
RA(8) <= ((A_FSB(9) AND ram/RASEL)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(18) AND NOT ram/RASEL));
RA(8) <= ((A_FSB(9) AND NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ram/RASEL)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(9) AND NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cs/nOverlay1 AND ram/RASEL)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(23) AND A_FSB(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(18) AND NOT ram/RASEL)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(18))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(22) AND A_FSB(18) AND cs/nOverlay1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(22) AND A_FSB(18) AND NOT cs/nOverlay1));
</td></tr><tr><td>
</td></tr><tr><td>
RA(9) <= ((A_FSB(20) AND ram/RASEL)
@ -398,40 +405,40 @@ FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;fsb/VPA_D <= ((EXP25_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(22) AND TimeoutB AND fsb/VPA AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(21) AND TimeoutB AND fsb/VPA AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (EXP16_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT cs/nOverlay1 AND NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT nADoutLE1 AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT nADoutLE1 AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT nADoutLE1 AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT nADoutLE1 AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (BERR_IOBS AND fsb/VPA AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (fsb/BERR0r AND fsb/VPA AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (fsb/BERR1r AND fsb/VPA AND NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (A_FSB(23) AND TimeoutB AND fsb/VPA AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$607)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$609)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(20) AND TimeoutB AND fsb/VPA AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$607));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT $OpTx$FX_DC$609));
</td></tr><tr><td>
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
</td></tr><tr><td>
@ -694,7 +701,7 @@ FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (fsb/BERR0r AND nDTACK_FSB)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (fsb/BERR1r AND nDTACK_FSB)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nAS_FSB AND NOT fsb/ASrf)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nDTACK_FSB AND NOT $OpTx$FX_DC$608));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nDTACK_FSB AND NOT $OpTx$FX_DC$610));
</td></tr><tr><td>
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;nDinLE_D <= ((iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd1)

86
cpld/XC95144XL/MXSE_html/fit/eqns.htm
View File

@ -3,7 +3,7 @@
<script src="paths.js"></script><script src="eqns.js"></script><script>
var design = "MXSE";
var device = "XC95144XL";
signals = new Array("ALE0M","ALE0S","BERR_IOBS","IOACT","IOBERR","IOL0","IOREQ","IORW0","IOU0","OpTxFX_DC607_SPECSIG","OpTxFX_DC608_SPECSIG","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RefAck","TimeoutA","TimeoutB","cntRefCnt0_SPECSIG","cntRefCnt1_SPECSIG","cntRefCnt2_SPECSIG","cntRefCnt3_SPECSIG","cntRefCnt4_SPECSIG","cntRefCnt5_SPECSIG","cntRefCnt6_SPECSIG","cntRefCnt7_SPECSIG","cntRefDone_SPECSIG","cntTimeoutBPre_SPECSIG","csnOverlay0_SPECSIG","csnOverlay1_SPECSIG","fsbASrf_SPECSIG","fsbBERR0r_SPECSIG","fsbBERR1r_SPECSIG","fsbReady0r_SPECSIG","fsbReady1r_SPECSIG","fsbReady2r_SPECSIG","fsbVPA_SPECSIG","iobmBERRrf_SPECSIG","iobmBERRrr_SPECSIG","iobmDTACKrf_SPECSIG","iobmDTACKrr_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmES4_SPECSIG","iobmETACK_SPECSIG","iobmEr2_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmRESrf_SPECSIG","iobmRESrr_SPECSIG","iobmVPArf_SPECSIG","iobmVPArr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOReady_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsOnce_SPECSIG","iobsPS_FSM_FFd1_SPECSIG","iobsPS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nRAMLWE","nRAMUWE","nRAS","nROMCS","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramBACTr_SPECSIG","ramOnce_SPECSIG","ramRAMDIS1_SPECSIG","ramRAMDIS2_SPECSIG","ramRAMReady_SPECSIG","ramRASEL_SPECSIG","ramRS_FSM_FFd1_SPECSIG","ramRS_FSM_FFd2_SPECSIG","ramRS_FSM_FFd3_SPECSIG");
signals = new Array("ALE0M","ALE0S","BERR_IOBS","IOACT","IOBERR","IOL0","IOREQ","IORW0","IOU0","OpTxFX_DC609_SPECSIG","OpTxFX_DC610_SPECSIG","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RefAck","TimeoutA","TimeoutB","cntRefCnt0_SPECSIG","cntRefCnt1_SPECSIG","cntRefCnt2_SPECSIG","cntRefCnt3_SPECSIG","cntRefCnt4_SPECSIG","cntRefCnt5_SPECSIG","cntRefCnt6_SPECSIG","cntRefCnt7_SPECSIG","cntRefDone_SPECSIG","cntTimeoutBPre_SPECSIG","csnOverlay0_SPECSIG","csnOverlay1_SPECSIG","fsbASrf_SPECSIG","fsbBERR0r_SPECSIG","fsbBERR1r_SPECSIG","fsbReady0r_SPECSIG","fsbReady1r_SPECSIG","fsbReady2r_SPECSIG","fsbVPA_SPECSIG","iobmBERRrf_SPECSIG","iobmBERRrr_SPECSIG","iobmDTACKrf_SPECSIG","iobmDTACKrr_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmES4_SPECSIG","iobmETACK_SPECSIG","iobmEr2_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmRESrf_SPECSIG","iobmRESrr_SPECSIG","iobmVPArf_SPECSIG","iobmVPArr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOReady_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsOnce_SPECSIG","iobsPS_FSM_FFd1_SPECSIG","iobsPS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nRAMLWE","nRAMUWE","nRAS","nROMCS","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramBACTr_SPECSIG","ramOnce_SPECSIG","ramRAMDIS1_SPECSIG","ramRAMDIS2_SPECSIG","ramRAMReady_SPECSIG","ramRASEL_SPECSIG","ramRS_FSM_FFd1_SPECSIG","ramRS_FSM_FFd2_SPECSIG","ramRS_FSM_FFd3_SPECSIG");
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","ON","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","ON","OFF","OFF","ON","ON");
sigTypes = new Array("D","D","T","D","T","D","D","T","D","","","","","","","","","","","","","","","D","T","T","T","T","T","T","T","T","T","T","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","T","D","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","T","D","D","D","D","D","","D","D","","","D","D","D","","D","D","","","","","","","D","T","","D","T","D","T","D","D","T","T","T");
@ -124,7 +124,7 @@
specSig["cntRefCnt0_SPECSIG"]=new Array("cnt/RefCnt<0>");
specSig["OpTxFX_DC607_SPECSIG"]=new Array("$OpTx$FX_DC$607");
specSig["OpTxFX_DC609_SPECSIG"]=new Array("$OpTx$FX_DC$609");
specSig["iobmEr_SPECSIG"]=new Array("iobm/Er");
@ -148,7 +148,7 @@
specSig["fsbReady2r_SPECSIG"]=new Array("fsb/Ready2r");
specSig["OpTxFX_DC608_SPECSIG"]=new Array("$OpTx$FX_DC$608");
specSig["OpTxFX_DC610_SPECSIG"]=new Array("$OpTx$FX_DC$610");
specSig["csnOverlay1_SPECSIG"]=new Array("cs/nOverlay1");
@ -248,45 +248,45 @@
pterms["FB2_18_1"]=new Array("E_IOB");
pterms["FB3_1_1"]=new Array("/A_FSB22_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_1_1"]=new Array("/A_FSB22_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_1_2"]=new Array("A_FSB21_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_1_2"]=new Array("A_FSB21_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_1_3"]=new Array("A_FSB23_SPECSIG","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_1_3"]=new Array("A_FSB23_SPECSIG","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_1_4"]=new Array("/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","csnOverlay1_SPECSIG","/fsbReady0r_SPECSIG","fsbVPA_SPECSIG","/ramRAMReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_1_4"]=new Array("/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","csnOverlay1_SPECSIG","/fsbReady0r_SPECSIG","fsbVPA_SPECSIG","/ramRAMReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_1_5"]=new Array("A_FSB22_SPECSIG","/A_FSB21_SPECSIG","A_FSB20_SPECSIG","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_1_5"]=new Array("A_FSB22_SPECSIG","/A_FSB21_SPECSIG","A_FSB20_SPECSIG","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_2_1"]=new Array("BERR_IOBS","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_2_1"]=new Array("BERR_IOBS","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_2_2"]=new Array("fsbBERR0r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_2_2"]=new Array("fsbBERR0r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_2_3"]=new Array("fsbBERR1r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_2_3"]=new Array("fsbBERR1r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_2_4"]=new Array("A_FSB23_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_2_4"]=new Array("A_FSB23_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_2_5"]=new Array("/A_FSB20_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_2_5"]=new Array("/A_FSB20_SPECSIG","TimeoutB","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_3_1"]=new Array("/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","/csnOverlay1_SPECSIG","/fsbReady0r_SPECSIG","fsbVPA_SPECSIG","/ramRAMReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_3_1"]=new Array("/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","/csnOverlay1_SPECSIG","/fsbReady0r_SPECSIG","fsbVPA_SPECSIG","/ramRAMReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_3_2"]=new Array("A_FSB14_SPECSIG","A_FSB22_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_3_2"]=new Array("A_FSB14_SPECSIG","A_FSB22_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_3_3"]=new Array("A_FSB13_SPECSIG","A_FSB22_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_3_3"]=new Array("A_FSB13_SPECSIG","A_FSB22_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_3_4"]=new Array("A_FSB14_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/nADoutLE1","/OpTxFX_DC607_SPECSIG");
pterms["FB3_3_4"]=new Array("A_FSB14_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/nADoutLE1","/OpTxFX_DC609_SPECSIG");
pterms["FB3_3_5"]=new Array("A_FSB13_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/nADoutLE1","/OpTxFX_DC607_SPECSIG");
pterms["FB3_3_5"]=new Array("A_FSB13_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","fsbVPA_SPECSIG","/iobsIOReady_SPECSIG","/nADoutLE1","/OpTxFX_DC609_SPECSIG");
pterms["FB3_4_1"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_4_1"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_4_2"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_4_2"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_4_3"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_4_3"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_4_4"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/TimeoutB","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","fsbReady1r_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_4_4"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/TimeoutB","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","fsbReady1r_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_4_5"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/TimeoutB","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","iobsIOReady_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_4_5"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/TimeoutB","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","iobsIOReady_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_5_1"]=new Array("nAS_FSB","/fsbASrf_SPECSIG");
@ -326,7 +326,7 @@
pterms["FB3_9_4"]=new Array("nAS_FSB","/fsbASrf_SPECSIG");
pterms["FB3_9_5"]=new Array("nDTACK_FSB","/OpTxFX_DC608_SPECSIG");
pterms["FB3_9_5"]=new Array("nDTACK_FSB","/OpTxFX_DC610_SPECSIG");
pterms["FB3_10_1"]=new Array("A_FSB13_SPECSIG","A_FSB22_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/fsbReady1r_SPECSIG","/iobsIOReady_SPECSIG","nDTACK_FSB");
@ -344,9 +344,9 @@
pterms["FB3_11_3"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","nDTACK_FSB");
pterms["FB3_11_4"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","fsbReady1r_SPECSIG","OpTxFX_DC608_SPECSIG");
pterms["FB3_11_4"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","fsbReady1r_SPECSIG","OpTxFX_DC610_SPECSIG");
pterms["FB3_11_5"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","iobsIOReady_SPECSIG","OpTxFX_DC608_SPECSIG");
pterms["FB3_11_5"]=new Array("A_FSB9_SPECSIG","A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/BERR_IOBS","/fsbBERR0r_SPECSIG","/fsbBERR1r_SPECSIG","iobsIOReady_SPECSIG","OpTxFX_DC610_SPECSIG");
pterms["FB3_12_1"]=new Array("/nWE_FSB","/iobsIORW1_SPECSIG");
@ -400,15 +400,15 @@
pterms["FB3_17_1"]=new Array("/nWE_FSB","/nAS_FSB");
pterms["FB3_18_1"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_18_1"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_18_2"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_18_2"]=new Array("A_FSB9_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_18_3"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_18_3"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","/csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_18_4"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_18_4"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","A_FSB14_SPECSIG","A_FSB13_SPECSIG","A_FSB12_SPECSIG","A_FSB11_SPECSIG","A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB3_18_5"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC607_SPECSIG");
pterms["FB3_18_5"]=new Array("A_FSB8_SPECSIG","A_FSB15_SPECSIG","/A_FSB14_SPECSIG","A_FSB13_SPECSIG","/A_FSB12_SPECSIG","/A_FSB11_SPECSIG","/A_FSB10_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","A_FSB21_SPECSIG","A_FSB20_SPECSIG","A_FSB19_SPECSIG","A_FSB18_SPECSIG","A_FSB17_SPECSIG","A_FSB16_SPECSIG","csnOverlay1_SPECSIG","/nWE_FSB","/TimeoutA","/fsbReady2r_SPECSIG","fsbVPA_SPECSIG","/OpTxFX_DC609_SPECSIG");
pterms["FB4_1_1"]=new Array("nAS_FSB","/fsbASrf_SPECSIG");
@ -808,12 +808,22 @@
pterms["FB7_7_3"]=new Array("/nRES");
pterms["FB7_8_1"]=new Array("A_FSB9_SPECSIG","ramRASEL_SPECSIG");
pterms["FB7_7_4"]=new Array("A_FSB9_SPECSIG","/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","csnOverlay1_SPECSIG","ramRASEL_SPECSIG");
pterms["FB7_8_1"]=new Array("A_FSB23_SPECSIG","A_FSB18_SPECSIG");
pterms["FB7_8_2"]=new Array("A_FSB18_SPECSIG","/ramRASEL_SPECSIG");
pterms["FB7_8_3"]=new Array("A_FSB22_SPECSIG","/A_FSB21_SPECSIG","A_FSB18_SPECSIG");
pterms["FB7_8_4"]=new Array("A_FSB22_SPECSIG","A_FSB18_SPECSIG","csnOverlay1_SPECSIG");
pterms["FB7_8_5"]=new Array("/A_FSB22_SPECSIG","A_FSB18_SPECSIG","/csnOverlay1_SPECSIG");
pterms["FB7_9_1"]=new Array("A_FSB21_SPECSIG");
pterms["FB7_9_2"]=new Array("A_FSB9_SPECSIG","/A_FSB23_SPECSIG","A_FSB22_SPECSIG","A_FSB21_SPECSIG","/csnOverlay1_SPECSIG","ramRASEL_SPECSIG");
pterms["FB7_10_1"]=new Array("cntTimeoutBPre_SPECSIG","nAS_FSB","/fsbASrf_SPECSIG");
pterms["FB7_10_2"]=new Array("/cntTimeoutBPre_SPECSIG","/nAS_FSB","/cntRefCnt0_SPECSIG","/cntRefCnt5_SPECSIG","/cntRefCnt6_SPECSIG","/cntRefCnt1_SPECSIG","/cntRefCnt2_SPECSIG","/cntRefCnt3_SPECSIG","/cntRefCnt4_SPECSIG","/cntRefCnt7_SPECSIG");
@ -1164,9 +1174,9 @@
gblclk["RefAck"]=new Array("CLK_FSB");
prld["RefAck"]="GND";
d2["OpTxFX_DC607_SPECSIG"]=new Array("FB1_18_1");
d2["OpTxFX_DC609_SPECSIG"]=new Array("FB1_18_1");
d2imp["OpTxFX_DC607_SPECSIG"]=new Array("1");
d2imp["OpTxFX_DC609_SPECSIG"]=new Array("1");
d2["iobmVPArr_SPECSIG"]=new Array("FB2_14_1");
@ -1322,9 +1332,9 @@
ceimp["csnOverlay1_SPECSIG"]=new Array("1");
prld["csnOverlay1_SPECSIG"]="GND";
d2["OpTxFX_DC608_SPECSIG"]=new Array("FB4_15_1","FB4_15_2");
d2["OpTxFX_DC610_SPECSIG"]=new Array("FB4_15_1","FB4_15_2");
d2imp["OpTxFX_DC608_SPECSIG"]=new Array("1","1");
d2imp["OpTxFX_DC610_SPECSIG"]=new Array("1","1");
d2["IOU0"]=new Array("FB4_16_1","FB4_16_2");
@ -1562,9 +1572,9 @@
rstimp["csnOverlay0_SPECSIG"]=new Array("1");
prld["csnOverlay0_SPECSIG"]="GND";
d2["RA8_SPECSIG"]=new Array("FB7_8_1","FB7_8_2");
d2["RA8_SPECSIG"]=new Array("FB7_8_1","FB7_8_2","FB7_8_3","FB7_8_4","FB7_8_5","FB7_7_4","FB7_9_2");
d2imp["RA8_SPECSIG"]=new Array("1","1");
d2imp["RA8_SPECSIG"]=new Array("1","1","1","1","1","1","1");
d2["RA10_SPECSIG"]=new Array("FB7_9_1");

2
cpld/XC95144XL/MXSE_html/fit/fbs.htm
View File

@ -59,7 +59,7 @@
<td align="center"><a href="javascript:showFBDetail('FB7');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
<td align="center">15 / 18</td>
<td align="center">39 / 54</td>
<td align="center">68 / 90</td>
<td align="center">73 / 90</td>
<td align="center">6 / 10</td>
</tr>
<tr>

2
cpld/XC95144XL/MXSE_html/fit/fbs_FB1.htm
View File

@ -214,7 +214,7 @@
<td align="center" width="10%">GCK</td>
</tr>
<tr>
<td align="center" width="10%"><a href="Javascript:showEqn('OpTxFX_DC607_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$607</a></td>
<td align="center" width="10%"><a href="Javascript:showEqn('OpTxFX_DC609_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$609</a></td>
<td align="center" width="10%">1</td>
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a>
</td>

4
cpld/XC95144XL/MXSE_html/fit/fbs_FB3.htm
View File

@ -215,8 +215,8 @@
</table></span></div>
<div id="tipBox"></div>
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
<li><a href="Javascript:showEqn('OpTxFX_DC607_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$607</a></li>
<li><a href="Javascript:showEqn('OpTxFX_DC608_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$608</a></li>
<li><a href="Javascript:showEqn('OpTxFX_DC609_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$609</a></li>
<li><a href="Javascript:showEqn('OpTxFX_DC610_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$610</a></li>
<li>A_FSB&lt;10&gt;</li>
<li>A_FSB&lt;11&gt;</li>
<li>A_FSB&lt;12&gt;</li>

2
cpld/XC95144XL/MXSE_html/fit/fbs_FB4.htm
View File

@ -181,7 +181,7 @@
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB&lt;2&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
</tr>
<tr>
<td align="center" width="10%"><a href="Javascript:showEqn('OpTxFX_DC608_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$608</a></td>
<td align="center" width="10%"><a href="Javascript:showEqn('OpTxFX_DC610_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$610</a></td>
<td align="center" width="10%">2</td>
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB4_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a>
</td>

4
cpld/XC95144XL/MXSE_html/fit/fbs_FB7.htm
View File

@ -105,8 +105,8 @@
</tr>
<tr>
<td align="center" width="10%"><a href="Javascript:showEqn('RA8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA&lt;8&gt;</a></td>
<td align="center" width="10%">2</td>
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB7_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a>
<td align="center" width="10%">7</td>
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_7_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_4</a> <a href="Javascript:showPT('FB7_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB7_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a> <a href="Javascript:showPT('FB7_8_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_3</a> <a href="Javascript:showPT('FB7_8_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_4</a> <a href="Javascript:showPT('FB7_8_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_5</a> <a href="Javascript:showPT('FB7_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a>
</td>
<td align="center" width="10%">MC8</td>
<td align="center" width="10%">STD</td>

8
cpld/XC95144XL/MXSE_html/fit/maplogic_00.htm
View File

@ -137,7 +137,7 @@
<td align="center">RESET</td>
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC607_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$607</a></td>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC609_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$609</a></td>
<td align="center">1</td>
<td align="center">2</td>
<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
@ -150,7 +150,7 @@
<td align="center"> </td>
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC608_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$608</a></td>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC610_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$610</a></td>
<td align="center">2</td>
<td align="center">5</td>
<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
@ -294,8 +294,8 @@
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('RA8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA&lt;8&gt;</a></td>
<td align="center">2</td>
<td align="center">3</td>
<td align="center">7</td>
<td align="center">7</td>
<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
<td align="center">MC8</td>
<td align="center">STD</td>

8
cpld/XC95144XL/MXSE_html/fit/maplogic_01.htm
View File

@ -241,7 +241,7 @@
<td align="center">RESET</td>
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC607_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$607</a></td>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC609_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$609</a></td>
<td align="center">1</td>
<td align="center">2</td>
<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
@ -579,7 +579,7 @@
<td align="center">RESET</td>
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC608_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$608</a></td>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC610_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$610</a></td>
<td align="center">2</td>
<td align="center">5</td>
<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
@ -1126,8 +1126,8 @@
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('RA8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA&lt;8&gt;</a></td>
<td align="center">2</td>
<td align="center">3</td>
<td align="center">7</td>
<td align="center">7</td>
<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
<td align="center">MC8</td>
<td align="center">STD</td>

8
cpld/XC95144XL/MXSE_html/fit/maplogic_02.htm
View File

@ -424,8 +424,8 @@
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('RA8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA&lt;8&gt;</a></td>
<td align="center">2</td>
<td align="center">3</td>
<td align="center">7</td>
<td align="center">7</td>
<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
<td align="center">MC8</td>
<td align="center">STD</td>
@ -813,7 +813,7 @@
<td align="center">RESET</td>
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC608_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$608</a></td>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC610_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$610</a></td>
<td align="center">2</td>
<td align="center">5</td>
<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
@ -935,7 +935,7 @@
<td align="center">RESET</td>
</tr>
<tr>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC607_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$607</a></td>
<td width="28%"><a href="javascript:showEqn('OpTxFX_DC609_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$FX_DC$609</a></td>
<td align="center">1</td>
<td align="center">2</td>
<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>

4
cpld/XC95144XL/MXSE_html/fit/summary.htm
View File

@ -30,7 +30,7 @@
<tr>
<td width="40%"> <b>Date</b>
</td>
<td width="60%">  2- 7-2022, 4:04AM</td>
<td width="60%">  2-14-2022, 7:35PM</td>
</tr>
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
@ -43,7 +43,7 @@
</tr>
<tr>
<td width="20%" align="center">105/144  (73%)</td>
<td width="20%" align="center">429/720  (60%)</td>
<td width="20%" align="center">434/720  (61%)</td>
<td width="20%" align="center">80/144  (56%)</td>
<td width="20%" align="center">67/81  (83%)</td>
<td width="20%" align="center">227/432  (53%)</td>

18
cpld/XC95144XL/MXSE_ngdbuild.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Feb 07 04:03:40 2022">
<application stringID="NgdBuild" timeStamp="Mon Feb 14 19:34:30 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -70,30 +70,30 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="169"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="54"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="255"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="256"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="107"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="108"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="12"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="169"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="60"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="255"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="256"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="107"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="108"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>

10
cpld/XC95144XL/MXSE_summary.html
View File

@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>MXSE Project Status (02/07/2022 - 04:05:11)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>MXSE Project Status (02/14/2022 - 19:36:00)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD>
@ -65,9 +65,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\MXSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Feb 7 03:26:05 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\MXSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Feb 7 04:08:55 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\MXSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Mon Feb 7 04:09:28 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\MXSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Feb 15 04:47:22 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\MXSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Feb 15 04:47:54 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\MXSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Tue Feb 15 04:48:27 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 02/07/2022 - 04:05:11</center>
<br><center><b>Date Generated:</b> 02/14/2022 - 19:36:00</center>
</BODY></HTML>

12
cpld/XC95144XL/MXSE_xst.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Mon Feb 07 03:25:37 2022">
<application stringID="Xst" timeStamp="Mon Feb 14 19:33:33 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -108,13 +108,13 @@
<item stringID="XST_IOS" value="67"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="605">
<item dataType="int" stringID="XST_AND2" value="170"/>
<item dataType="int" stringID="XST_AND3" value="24"/>
<item dataType="int" stringID="XST_BELS" value="607">
<item dataType="int" stringID="XST_AND2" value="169"/>
<item dataType="int" stringID="XST_AND3" value="25"/>
<item dataType="int" stringID="XST_AND4" value="14"/>
<item dataType="int" stringID="XST_GND" value="6"/>
<item dataType="int" stringID="XST_INV" value="255"/>
<item dataType="int" stringID="XST_OR2" value="107"/>
<item dataType="int" stringID="XST_INV" value="256"/>
<item dataType="int" stringID="XST_OR2" value="108"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="12"/>
</item>

6
cpld/XC95144XL/WarpSE.gise
View File

@ -59,6 +59,7 @@
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1644222322" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1644222321">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1644222322" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="167449203504654628" xil_pn:start_ts="1644222322">
<status xil_pn:value="SuccessfullyRun"/>
@ -67,6 +68,7 @@
<transform xil_pn:end_ts="1644222367" xil_pn:in_ck="-7042198571556068688" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-2899378119827487496" xil_pn:start_ts="1644222322">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<outfile xil_pn:name="MXSE.lso"/>
<outfile xil_pn:name="MXSE.ngc"/>
<outfile xil_pn:name="MXSE.ngr"/>
@ -86,6 +88,7 @@
<transform xil_pn:end_ts="1644224623" xil_pn:in_ck="1136913611493600791" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1644224591">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="MXSE.bld"/>
<outfile xil_pn:name="MXSE.ngd"/>
<outfile xil_pn:name="MXSE_ngdbuild.xrpt"/>
@ -96,6 +99,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="MXSE.gyd"/>
<outfile xil_pn:name="MXSE.mfd"/>
<outfile xil_pn:name="MXSE.nga"/>
@ -113,11 +117,13 @@
<transform xil_pn:end_ts="1644224711" xil_pn:in_ck="3398601141924" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1644224694">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1644224548" xil_pn:in_ck="1136913611493600792" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1644224548">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>

169
cpld/XC95144XL/WarpSE.xise
View File

@ -49,131 +49,57 @@
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc95144xl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|MXSE" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../MXSE.v" xil_pn:valueState="non-default"/>
@ -185,15 +111,8 @@
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
@ -205,25 +124,14 @@
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@ -231,16 +139,11 @@
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@ -248,75 +151,35 @@
<property xil_pn:name="Output File Name" xil_pn:value="MXSE" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="TQ100" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MXSE_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MXSE_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MXSE_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MXSE_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@ -325,33 +188,18 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -361,35 +209,22 @@
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->

2
cpld/XC95144XL/_ngo/netlist.lst
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@ -1,2 +1,2 @@
\\192.168.64.1\Repos\Warp-SE\cpld\XC95144XL\MXSE.ngc 1644222364
\\192.168.64.1\Repos\Warp-SE\cpld\XC95144XL\MXSE.ngc 1644885239
OK

9
cpld/XC95144XL/_xmsgs/hprep6.xmsgs Normal file
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@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

3
cpld/XC95144XL/_xmsgs/pn_parser.xmsgs
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@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;//192.168.64.1/Repos/Warp-SE/cpld/RAM.v&quot; into library work</arg>
</msg>
</messages>

4
cpld/XC95144XL/iseconfig/MXSE.xreport
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@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2022-02-07T03:25:13</DateModified>
<DateModified>2022-02-14T19:23:34</DateModified>
<ModuleName>MXSE</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/iseconfig/MXSE.xreport</SavedFilePath>
<ImplementationReportsDirectory>//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL</ImplementationReportsDirectory>
<ImplementationReportsDirectory>//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
<DateInitialized>2022-02-07T03:25:12</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>

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cpld/XC95144XL/xlnx_auto_0_xdb/cst.xbcd
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cpld/XC95144XL/xst/work/hdllib.ref
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@ -1,7 +1,7 @@
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1644222338
MO CS NULL ../CS.v vlg22/_c_s.bin 1644222338
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1644222338
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1644222338
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1644222338
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1644222337
MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1644222338
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1644885214
MO CS NULL ../CS.v vlg22/_c_s.bin 1644885214
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1644885214
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1644885214
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1644885214
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1644885214
MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1644885214

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