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Revert "idk" 

This reverts commit aa30aa8a55.
This commit is contained in:
Zane Kaminski 2023-07-15 23:21:44 -04:00
parent 2d12028bd3
commit e68cdda869
8 changed files with 121 additions and 141 deletions
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21
Prog.kicad_sch
View File

@ -863,6 +863,9 @@
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62
WarpSE.kicad_pcb
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@ -19885,42 +19867,44 @@
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(segment (start 145.415 127.254) (end 194.254 127.254) (width 0.15) (layer "F.Cu") (net 248) (tstamp 1ff0863b-ab05-4483-afe7-2556d8435cf3))
(segment (start 206.375 59.69) (end 208.534 61.849) (width 0.15) (layer "F.Cu") (net 248) (tstamp 2bbf3772-d5de-4ffa-b838-85a49c778430))
(segment (start 126.9125 104.1) (end 129.25 104.1) (width 0.15) (layer "F.Cu") (net 248) (tstamp 3b5d5afa-feae-4318-9c64-e7e95f5e7948))
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(segment (start 204.47 60.3885) (end 205.1685 59.69) (width 0.15) (layer "F.Cu") (net 248) (tstamp 4bd7dcd3-90da-4323-8ca9-5ed74bfedb07))
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(segment (start 199.263 62.23) (end 203.835 62.23) (width 0.15) (layer "F.Cu") (net 248) (tstamp 5513cbc3-d39b-4ac7-9b4e-b99df837a810))
(segment (start 130.81 105.66) (end 130.81 112.649) (width 0.15) (layer "F.Cu") (net 248) (tstamp 6a2bb87e-7436-4d0a-ad9b-1db494925607))
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(segment (start 129.25 104.1) (end 130.81 105.66) (width 0.15) (layer "F.Cu") (net 248) (tstamp a11da13b-7c7a-4d73-a874-b7a8a8dfed45))
(segment (start 126.9125 104.1) (end 129.25 104.1) (width 0.15) (layer "F.Cu") (net 248) (tstamp bc93f86b-52a4-4edf-b98c-01b50284dc56))
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(segment (start 205.1685 59.69) (end 206.375 59.69) (width 0.15) (layer "F.Cu") (net 248) (tstamp c61285d2-97f9-4667-afbc-fa1e7ba0d82c))
(segment (start 208.534 130.937) (end 208.534 63.754) (width 0.15) (layer "F.Cu") (net 248) (tstamp e23e8045-2686-4d32-8f34-714035d144e5))
(segment (start 198.733 61.7) (end 199.263 62.23) (width 0.15) (layer "F.Cu") (net 248) (tstamp e4a56b0b-34d7-4a98-9b11-9962a8278547))
(segment (start 208.534 61.849) (end 208.534 62.611) (width 0.15) (layer "F.Cu") (net 248) (tstamp eb9b1d68-f86d-4789-9cad-79bde1ad4457))
(segment (start 197.2 61.7) (end 198.733 61.7) (width 0.15) (layer "F.Cu") (net 248) (tstamp fae077df-760b-4928-a536-2a427e38c4c8))
(segment (start 129.25 104.1) (end 130.81 105.66) (width 0.15) (layer "F.Cu") (net 248) (tstamp fd5830c0-d19e-429f-a6e6-b666e1490a60))
(segment (start 196.21 59.69) (end 195.75 60.15) (width 0.15) (layer "F.Cu") (net 250) (tstamp 01ed8625-60ab-4587-a1ed-16e5858dbdd7))
(segment (start 194.9 59.7) (end 194.9 58.75) (width 0.15) (layer "F.Cu") (net 250) (tstamp 0dfc37d1-ce00-4819-8807-80114891a65a))
(segment (start 195.75 60.15) (end 195.35 60.15) (width 0.15) (layer "F.Cu") (net 250) (tstamp 1bce780c-1287-40c7-84cc-40c4a1f655e7))
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(segment (start 144.907 128.27) (end 130.048 113.411) (width 0.15) (layer "F.Cu") (net 251) (tstamp 0dcf2c8d-3bd2-4f32-bbc1-5e69d006e961))
(segment (start 198.342 132.842) (end 193.77 128.27) (width 0.15) (layer "F.Cu") (net 251) (tstamp 25128116-09b9-44b9-8866-b89dfaac65d5))
(segment (start 209.55 131.445) (end 208.153 132.842) (width 0.15) (layer "F.Cu") (net 251) (tstamp 0214fbc5-e799-4490-bd06-06432fb66382))
(segment (start 197.2 58.65) (end 198.3345 58.65) (width 0.15) (layer "F.Cu") (net 251) (tstamp 2e76d93e-34ae-4853-a1f0-cb784e084560))
(segment (start 209.55 60.1345) (end 209.55 131.445) (width 0.15) (layer "F.Cu") (net 251) (tstamp 4d1033e1-95c0-4b87-bdfe-8355cd3b720b))
(segment (start 209.55 60.1345) (end 209.55 61.2775) (width 0.15) (layer "F.Cu") (net 251) (tstamp 2feed0f4-a5b3-4356-ad96-ee3deab0196c))
(segment (start 193.77 128.27) (end 144.907 128.27) (width 0.15) (layer "F.Cu") (net 251) (tstamp 45c68b4c-e33d-4171-acfb-11666db28019))
(segment (start 209.55 62.23) (end 209.55 131.445) (width 0.15) (layer "F.Cu") (net 251) (tstamp 4b195cef-34cc-462a-949d-2b419e6a2e43))
(segment (start 199.8345 57.15) (end 206.5655 57.15) (width 0.15) (layer "F.Cu") (net 251) (tstamp 535d585a-563c-4fe4-8755-baea525ccf61))
(segment (start 128.25 104.6) (end 126.9125 104.6) (width 0.15) (layer "F.Cu") (net 251) (tstamp 55672923-9dbe-4829-ab80-9f35c5eac269))
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(segment (start 144.907 128.27) (end 130.048 113.411) (width 0.15) (layer "F.Cu") (net 251) (tstamp 5644422e-5864-4f0b-882c-06a24d5b1ba0))
(segment (start 206.5655 57.15) (end 209.55 60.1345) (width 0.15) (layer "F.Cu") (net 251) (tstamp 5c6f039d-78dd-4d56-99e3-f88e22aa4317))
(segment (start 130.048 113.411) (end 130.048 106.398) (width 0.15) (layer "F.Cu") (net 251) (tstamp 6cb3ed81-c7ac-42c3-aea9-969280b5b737))
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(segment (start 130.048 106.398) (end 128.25 104.6) (width 0.15) (layer "F.Cu") (net 251) (tstamp a3df2ca6-da3d-42a5-add5-152ed1aa7297))
(segment (start 208.153 132.842) (end 198.342 132.842) (width 0.15) (layer "F.Cu") (net 251) (tstamp a7a74e02-5abc-4888-8547-a4bd2e048056))
(segment (start 128.25 104.6) (end 126.9125 104.6) (width 0.15) (layer "F.Cu") (net 251) (tstamp ac8ec369-ded1-469b-a93b-4d3dc9fd344b))
(segment (start 198.342 132.842) (end 193.77 128.27) (width 0.15) (layer "F.Cu") (net 251) (tstamp 7434723a-dc4b-4af0-989a-ba76d98ad5a6))
(segment (start 198.3345 58.65) (end 199.8345 57.15) (width 0.15) (layer "F.Cu") (net 251) (tstamp aecdc8ca-df98-40eb-acc2-46fd3a9527eb))
(segment (start 209.55 131.445) (end 208.153 132.842) (width 0.15) (layer "F.Cu") (net 251) (tstamp c8568188-6d5a-49a4-bef7-536ea95d9890))
(segment (start 130.048 106.398) (end 128.25 104.6) (width 0.15) (layer "F.Cu") (net 251) (tstamp b322e8ed-a3e6-4b39-9944-fcc81714e2da))
(segment (start 130.048 113.411) (end 130.048 106.398) (width 0.15) (layer "F.Cu") (net 251) (tstamp ea85e668-8748-498b-9d7f-e7253b440a06))
(segment (start 195.55 57.05) (end 197.2 57.05) (width 0.15) (layer "F.Cu") (net 252) (tstamp eaa8797e-60e4-4614-abe2-d09280a0367b))
(segment (start 197.2 63.3) (end 195.55 63.3) (width 0.15) (layer "F.Cu") (net 253) (tstamp 11d6792a-5ca8-42c6-bfff-7bd49b91cd6e))
(segment (start 187.5 124.85) (end 187.5 123.2) (width 0.15) (layer "F.Cu") (net 254) (tstamp 3bea487f-2fe2-4a4b-b038-c63cf44060f5))

71
cpld/CNT.v
View File

@ -1,23 +1,22 @@
module CNT(
/* FSB clock, C8M clock, E clock inputs */
input CLK, input C8M, input E,
/* FSB clock and E clock inputs */
input CLK, input E,
/* Refresh request */
output RefClk,
output reg RefReq, output reg RefUrg,
/* Reset, button */
output reg nRESout, input nIPL2,
/* Mac PDS bus master control outputs */
output reg AoutOE, output reg nBR_IOB,
/* Sound QoS */
input BACT, input SndRAMCSWR, output reg QoSReady);
input BACT, input nWE,
input SndROMCS, input SndRAMCSWR, input RAMCS,
output reg QoSReady);
/* E clock synchronization */
reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
reg [1:0] Er;
wire EFall = Er[1] && !Er[0];
/* C8M clock synchronization */
reg [1:0] C8Mr; always @(posedge CLK) C8Mr[1:0] <= { C8Mr[0], C8M };
wire C8MFall = C8Mr[1] && !C8Mr[0];
always @(posedge CLK) Er[1:0] <= { Er[0], E };
/* NMI button synchronization */
reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
@ -47,50 +46,37 @@ module CNT(
if (EFall) begin
if (TimerTC) Timer <= 0;
else Timer <= Timer+1;
RefUrg <= Timer==8 || Timer==9;
RefReq <= Timer!=10;
TimerTC <= Timer==9;
end
end
assign RefClk = Timer[3];
/* Long timer counts from 0 to 4095.
* 4096 states == 57.516 ms */
/* During init (IS!=3) long timer counts from 0 to 4095.
* 4096 states == 57.516 ms
* During operation (IS==3) long timer counts from 0 to 3
* starting at first sound RAM access.
* Period is 28.124 us - 42.240 us */
reg [11:0] LTimer;
reg LTimerTC;
always @(posedge CLK) begin
if (EFall && TimerTC) LTimer <= LTimer+1;
if (IS==3) begin
LTimer[11:2] <= 0;
if (BACT && SndRAMCSWR) LTimer[1:0] <= 1;
else if (LTimer==0) LTimer[1:0] <= 0;
else if (EFall && TimerTC) LTimer[1:0] <= LTimer+1;
end else if (EFall && TimerTC) LTimer <= LTimer+1;
LTimerTC <= LTimer[11:0]==12'hFFE;
end
/* Sound QoS trigger
* Sound timer counts from 1 to 3
* starting at first sound RAM access.
* Period is 28.124 us - 42.240 us */
reg [1:0] STimer;
reg SndSlowEN;
always @(posedge CLK) begin
if (BACT && SndRAMCSWR) begin
STimer <= 1;
SndSlowEN <= 1;
end else if (STimer==0) begin
STimer <= 0;
SndSlowEN <= 0;
end else if (EFall && TimerTC) begin
LTimer <= LTimer+1;
SndSlowEN <= STimer!=3;
end
end
/* Sound QoS */
wire SndSlowEN = LTimer[1:0]!=0;
reg [6:0] Credits;
reg [3:0] WS = 0;
always @(posedge CLK) begin
if (!SndSlowEN) Credits <= 8;
else if (!C8MFall && !FSBW) Credits <= Credits+1;
else if ( C8MFall && !FSBW) Credits <= Credits;
else if (!C8MFall && FSBW) Credits <= Credits;
else if ( C8MFall && FSBW) Credits <= Credits-1;
if (!BACT) WS <= 0;
else WS <= WS+1;
QoSReady <= (LTimer[1:0]==0) || (BACT && (
QoSReady || WS==15 || !nWE || (!RAMCS && !SndROMCS)));
end
always @(posedge CLK) if (!BACT || !QoSReady) QoSReady <= Credits[6:3]==0;
/* Startup sequence state control */
wire ISTC = EFall && TimerTC && LTimerTC;
@ -116,4 +102,5 @@ module CNT(
end
endcase
end
endmodule

16
cpld/CS.v
View File

@ -3,15 +3,13 @@ module CS(
input [23:08] A, input CLK, input nRES, input nWE,
/* AS cycle detection */
input BACT,
/* Overlay */
output Overlay,
/* Device select outputs */
output IOCS, output IOPWCS, output IACS,
output ROMCS, output ROMCS4X,
output ROMCS, output ROMCS4X, output SndROMCS,
output RAMCS, output RAMCS0X, output SndRAMCSWR);
/* Overlay control */
reg nOverlay = 0; assign Overlay = !nOverlay;
reg nOverlay = 0; wire Overlay = !nOverlay;
always @(posedge CLK) begin
if (!BACT && !nRES) nOverlay <= 0;
else if (BACT && ROMCS4X) nOverlay <= 1;
@ -19,12 +17,14 @@ module CS(
/* ROM select signals */
assign ROMCS4X = A[23:20]==4'h4;
assign ROMCS = Overlay || ROMCS4X;
assign ROMCS = (A[23:20]==4'h0 && Overlay) || ROMCS4X;
assign SndROMCS = ROMCS4X &&
(A[20:8]==12'h36C || A[20:8]==12'h36D || A[20:8]==12'h36F);
/* RAM select signals */
assign RAMCS0X = A[23:22]==2'b00;
assign RAMCS = RAMCS0X && !Overlay;
wire VidRAMCSWR64k = A[23:16]==8'h3F && !nWE; // 3F0000-3FFFFF
wire VidRAMCSWR64k = RAMCS0X && !nWE && A[23:16]==8'h3F; // 3F0000-3FFFFF
wire VidRAMCSWR = VidRAMCSWR64k && (
A[15:12]==4'h2 || // 1792 bytes RAM, 2304 bytes video
A[15:12]==4'h3 || // 4096 bytes video
@ -56,6 +56,6 @@ module CS(
A[23:20]==4'h6 || // empty
A[23:20]==4'h5 || // SCSI
(A[23:20]==4'h4 && Overlay) || // ROM once
VidRAMCSWR64k; // Write to video RAM
assign IOPWCS = VidRAMCSWR64k;
VidRAMCSWR; // Write to video RAM
assign IOPWCS = VidRAMCSWR;
endmodule

11
cpld/FSB.v
View File

@ -2,11 +2,11 @@ module FSB(
/* MC68HC000 interface */
input FCLK, input nAS, output reg nDTACK, output reg nVPA,
/* AS cycle detection */
output BACT, output reg [3:1] BACTr, output reg WS,
output BACT,
/* Ready inputs */
input ROMCS,
input RAMCS, input RAMReady,
input IOPWCS, input IOPWReady, input IOReady,
input IOPWCS, input IOPWReady, input IONPReady,
input QoSReady,
/* Interrupt acknowledge select */
input IACS);
@ -15,13 +15,12 @@ module FSB(
reg ASrf = 0;
always @(negedge FCLK) begin ASrf <= !nAS; end
assign BACT = !nAS || ASrf; // BACT - bus active
always @(posedge FCLK) BACTr[3:1] <= { BACTr[2:1], BACT };
always @(posedge FCLK) WS <= BACTr[3:1]==3'b111 && BACT;
/* DTACK/VPA control */
wire Ready = (QoSReady && RAMCS && RAMReady && !IOPWCS) ||
( RAMCS && RAMReady && IOPWCS && IOPWReady) ||
(QoSReady && ROMCS) || (IOReady);
(QoSReady && RAMCS && RAMReady && IOPWCS && IOPWReady) ||
(QoSReady && ROMCS) || (IONPReady);
always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
always @(posedge FCLK, posedge nAS) begin
if (nAS) nVPA <= 1;

19
cpld/IOBS.v
View File

@ -4,9 +4,9 @@ module IOBS(
/* AS cycle detection */
input BACT,
/* Select signals */
input IOCS, input IOPWCS, input Overlay,
input IOCS, input IOPWCS, input ROMCS,
/* FSB cycle termination outputs */
output reg IOReady, output IOPWReady, output reg nBERR_FSB,
output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
/* Read data OE control */
output nDinOE,
/* IOB master controller interface */
@ -25,7 +25,7 @@ module IOBS(
wire IODONE = IODONEr;
/* Read data OE control */
assign nDinOE = !(!nAS && IOCS && nWE && !Overlay);
assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
/* I/O transfer state
* TS0 - I/O bridge idle:
@ -47,7 +47,7 @@ module IOBS(
always @(posedge CLK) begin // ALE and R/W load control
// If write currently posting (TS!=0),
// I/O selected, and FIFO secondary level empty
if (BACT && !ALE1 && !Sent && IOPWCS && TS!=0) begin
if (BACT && IOCS && !ALE1 && !Sent && IOPWCS && TS!=0) begin
// Latch R/W now but latch address and LDS/UDS next cycle
IORW1 <= nWE;
Load1 <= 1;
@ -122,17 +122,14 @@ module IOBS(
/* Sent control */
always @(posedge CLK) begin
if (!BACT) Sent <= 0;
else if (IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
end
/* Posted write ready */
/* Nonposted and posted ready */
assign IOPWReady = !ALE1; // Posted write reaedy
/* Nonposted ready / posted write submitted ready continuation */
always @(posedge CLK) begin // Nonposted read/write ready
if (!BACT) IOReady <= 0;
else if (Sent && IODONE) IOReady <= 1;
else if (IOPWCS && !ALE1) IOReady <= 1;
if (!BACT) IONPReady <= 0;
else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
end
/* BERR control */

25
cpld/RAM.v
View File

@ -3,16 +3,17 @@ module RAM(
input CLK, input [21:1] A, input nWE,
input nAS, input nLDS, input nUDS, input nDTACK,
/* AS cycle detection */
input BACT, input [3:1] BACTr,
input BACT,
/* Select and ready signals */
input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady,
/* Refresh Counter Interface */
input RefClk,
input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */
output [11:0] RA, output nRAS, output reg nCAS,
output nLWE, output nUWE, output reg nOE, output nROMCS, output nROMWE);
/* BACT and /DTACK registration */
reg BACTr; always @(posedge CLK) BACTr <= BACT;
reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
/* RAM control state */
@ -23,19 +24,13 @@ module RAM(
reg RASrf = 0;
/* Refresh command generation */
reg nRefClkR; always @(posedge CLK) nRefClkR <= !RefClk;
reg RefReq;
reg RefUrg;
reg RefDone; // Refresh done "remember"
always @(posedge CLK) begin
if (!nRefClkR && !RefClk) begin
RefReq <= 1;
else if (nRefClkR && RefClk) begin
RefUrg <= RefReq;
else if (RS[2]) beign
RefReq <= 0;
RefUrg <= 0;
end
if (!RefReqIn && !RefUrgIn) RefDone <= 0;
else if (RS[2]) RefDone <= 1;
end
wire RefReq = RefReqIn && !RefDone;
wire RefUrg = RefUrgIn && !RefDone;
/* RAM control signals */
assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
@ -47,7 +42,7 @@ module RAM(
assign nROMWE = !(!nAS && !nWE);
/* Shared ROM and RAM /OE control */
always @(posedge CLK) nOE <= !(BACT && nWE && !(BACTr[1] && DTACKr));
always @(posedge CLK) nOE <= !(BACT && nWE && !(BACTr && DTACKr));
/* RAM address mux (and ROM address on RA8) */
// RA11 doesn't do anything so both should be identical.
@ -67,7 +62,7 @@ module RAM(
assign RA[00] = !RASEL ? A[09] : A[01];
wire RS0toRef = // Refresh during first clock of non-RAM access
(RefReq && BACT && !BACTr[1] && !RAMCS0X) ||
(RefReq && BACT && !BACTr && !RAMCS0X) ||
// Urgent refresh while bus inactive
(RefUrg && !BACT) ||
// Urgent refresh during non-RAM access

37
cpld/WarpSE.v
View File

@ -50,27 +50,22 @@ module WarpSE(
/* AS cycle detection */
wire BACT;
wire [3:1] BACTr;
wire WS;
/* Refresh request clock */
wire RefClk;
/* Refresh request/ack signals */
wire RefReq, RefUrg;
/* FSB chip select signals */
wire Overlay;
wire IOCS, IOPWCS, IACS;
wire ROMCS, ROMCS4X, SndROMCS;
wire RAMCS, RAMCS0X, SndRAMCSWR;
CS cs(
/* MC68HC000 interface */
A_FSB[23:08], FCLK, nRESin, nWE_FSB,
/* /AS cycle detection */
/* AS cycle detection */
BACT,
/* Overlay */
Overlay,
/* Device select outputs */
IOCS, IOPWCS, IACS,
ROMCS, ROMCS4X,
ROMCS, ROMCS4X, SndROMCS,
RAMCS, RAMCS0X, SndRAMCSWR);
wire RAMReady;
@ -79,16 +74,16 @@ module WarpSE(
FCLK, A_FSB[21:1], nWE_FSB,
nAS_FSB, nLDS_FSB, nUDS_FSB, nDTACK_FSB,
/* AS cycle detection */
BACT, BACTr,
BACT,
/* Select and ready signals */
RAMCS, RAMCS0X, ROMCS, RAMReady,
/* Refresh Counter Interface */
RefClk,
RefReq, RefUrg,
/* DRAM and NOR flash interface */
RA[11:0], nRAS, nCAS,
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
wire IOReady, IOPWReady;
wire IONPReady, IOPWReady;
wire IORDREQ, IOWRREQ;
wire IOL0, IOU0;
wire ALE0S, ALE0M, ALE1;
@ -101,9 +96,9 @@ module WarpSE(
/* AS cycle detection */
BACT,
/* Select signals */
IOCS, IOPWCS, Overlay,
IOCS, IOPWCS, ROMCS,
/* FSB cycle termination outputs */
IOReady, IOPWReady, nBERR_FSB,
IONPReady, IOPWReady, nBERR_FSB,
/* Read data OE control */
nDinOE,
/* IOB Master Controller Interface */
@ -134,26 +129,28 @@ module WarpSE(
wire QoSReady;
CNT cnt(
/* FSB clock, C8M clock, E clock inputs */
FCLK, C8M, E,
/* FSB clock and E clock inputs */
FCLK, E,
/* Refresh request */
RefClk,
RefReq, RefUrg,
/* Reset, button */
nRESout, nIPL2,
/* Mac PDS bus master control outputs */
AoutOE, nBR_IOB,
/* Sound QoS */
BACT, SndRAMCSWR, QoSReady);
BACT, nWE_FSB,
SndROMCS, SndRAMCSWR, RAMCS0X,
QoSReady);
FSB fsb(
/* MC68HC000 interface */
FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
/* FSB cycle detection */
BACT, BACTr, WS,
BACT,
/* Ready inputs */
ROMCS4X,
RAMCS0X, RAMReady,
IOPWCS, IOPWReady, IOReady,
IOPWCS, IOPWReady, IONPReady,
QoSReady,
/* Interrupt acknowledge select */
IACS);