Add sound QoS back

cpld/CNT.v

@@ -6,13 +6,18 @@ module CNT(
 	/* Reset, button */
 	output reg nRESout, input nIPL2, 
 	/* Mac PDS bus master control outputs */
-	output reg AoutOE, output reg nBR_IOB);
+	output reg AoutOE, output reg nBR_IOB,
+	/* Sound QoS */
+	input BACT, input SndRAMCSWR, output QoSReady);
 	
 	/* E clock synchronization */
 	reg [1:0] Er;
 	wire EFall = Er[1] && !Er[0];
 	always @(posedge CLK) Er[1:0] <= { Er[0], E };
 	
+	/* NMI button synchronization */
+	reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
+
 	/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
     *	Refresh timer sequence
 	 * |  Timer  | RefReq |   RefUrg  |
@@ -41,40 +46,61 @@ module CNT(
 		end
 	end
 	
-	/* Long timer counts from 0 to 8191 -- 8192 states == 115.033 ms */
+	/* During init (IS!=3) long timer counts from 0 to 8191.
+	 * 8192 states == 115.033 ms 
+	 * During operation (IS==3) long timer counts from 0 to 1023
+	 * starting at first sound RAM access.
+	 * 8192 states == 14.379 ms */
 	reg [12:0] LTimer;
 	reg LTimerTC;
 	always @(posedge CLK) begin
 		if (EFall && TimerTC) begin
-			LTimer <= LTimer+1;
+			if (IS==3) begin
+				LTimer[12:10] <= 3'b000;
+				if (LTimer==0 && BACT && VidRAMCSWR) LTimer <= 1;
+				else if (LTimer==0) LTimer <= 0;
+				else LTimer[9:0] <= LTimer+1;
+			end else LTimer <= LTimer+1;
 			LTimerTC <= LTimer[12:0]==13'h1FFE;
 		end
 	end
 
-	reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
+	/* Sound QoS */
+	reg [3:0] WS = 0;
+	always @(posedge CLK) begin
+		if (BACT) begin
+			if (QoSReady) QoSReady <= 1;
+			else if (WS==12) QoSReady <= 1;
+			WS <= WS+1;
+		end else begin
+			if (LTimer!=0) QoSReady <= 0;
+			else QoSReady <= 1;
+			WS <= 0;
+		end
+	end
 
 	/* Startup sequence control */
-	reg [1:0] INITS = 0;
-	wire INITSTC = EFall && TimerTC && LTimerTC;
+	reg [1:0] IS = 0;
+	wire ISTC = EFall && TimerTC && LTimerTC;
 	always @(posedge CLK) begin
-		case (INITS[1:0])
+		case (IS[1:0])
 			2'h0: begin
 				AoutOE <= 0; // Tristate PDS address and control
 				nRESout <= 0; // Hold reset low
 				nBR_IOB <= 0; // Default to request bus
-				if (INITSTC) INITS <= 1;
+				if (ISTC) IS <= 1;
 			end 2'h1: begin
 				AoutOE <= 0;
 				nRESout <= 0;
 				nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
-				if (INITSTC && nIPL2r) INITS <= 2;
+				if (ISTC && nIPL2r) IS <= 2;
 			end 2'h2: begin
 				AoutOE <= !nBR_IOB;
 				nRESout <= 0;
-				if (INITSTC) INITS <= 3;
+				if (ISTC) IS <= 3;
 			end 2'h3: begin
 				nRESout <= 1; // Release reset
-				INITS <= 3;
+				IS <= 3;
 			end
 		endcase
 	end

cpld/CS.v

@@ -88,25 +88,25 @@ module CS(
 			(A[11:8]==4'hC && !A[7]) ||
 			 A[11:8]==4'hD ||
 			 A[11:8]==4'hE ||
-			 A[11:8]==4'hF));
+			 A[11:8]==4'hF)));
 	assign SndRAMCSWR = VidRAMCSWR64k && (
 		((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) ||
 		((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
 
 	/* Select signals - IOB domain */
-	assign IACS =  (A[23:20]==4'hF) && (A[19:18]==2'b11); // IACK
-	assign IOCS =  (A[23:20]==4'hF) || // IACK
-				   (A[23:20]==4'hE) || // VIA
-				   (A[23:20]==4'hD) || // IWM
-				   (A[23:20]==4'hC) || // empty / fast ROM
-				   (A[23:20]==4'hB) || // SCC write
-				   (A[23:20]==4'hA) || // empty
-				   (A[23:20]==4'h9) || // SCC read/reset
-				   (A[23:20]==4'h8) || // empty
-				   (A[23:20]==4'h7) || // empty
-				   (A[23:20]==4'h6) || // empty
-				   (A[23:20]==4'h5) || // SCSI
-				  ((A[23:20]==4'h4) && Overlay) || // ROM once
+	assign IACS =  A[23:16]==4'hFF; // IACK
+	assign IOCS =  A[23:20]==4'hF || // IACK
+				   A[23:20]==4'hE || // VIA
+				   A[23:20]==4'hD || // IWM
+				   A[23:20]==4'hC || // empty / fast ROM
+				   A[23:20]==4'hB || // SCC write
+				   A[23:20]==4'hA || // empty
+				   A[23:20]==4'h9 || // SCC read/reset
+				   A[23:20]==4'h8 || // empty
+				   A[23:20]==4'h7 || // empty
+				   A[23:20]==4'h6 || // empty
+				   A[23:20]==4'h5 || // SCSI
+				  (A[23:20]==4'h4 && Overlay) || // ROM once
 				    VidRAMCSWR; // Write to video RAM
 	assign IOPWCS = VidRAMCSWR;
 endmodule

cpld/FSB.v

@@ -7,7 +7,8 @@ module FSB(
 	input ROMCS,
 	input RAMCS, input RAMReady,
 	input IOPWCS, input IOPWReady, input IONPReady,
-	/* Interrupt acknowledge select */
+	input QoSReady,
+	/* Interrupt acknowledge select */z
 	input IACS);
 
 	/* AS cycle detection */
@@ -17,9 +18,10 @@ module FSB(
 
 
 	/* DTACK/VPA control */
-	wire Ready = (RAMCS && RAMReady && !IOPWCS) ||
+	wire Ready = QoSReady &&
+				((RAMCS && RAMReady && !IOPWCS) ||
 				 (RAMCS && RAMReady &&  IOPWCS && IOPWReady) ||
-				 (ROMCS) || (IONPReady);
+				 (ROMCS) || (IONPReady));
 	always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
 	always @(posedge FCLK, posedge nAS) begin
 		if (nAS) nVPA <= 1;

cpld/WarpSE.v

@@ -59,7 +59,7 @@ module WarpSE(
 	/* FSB chip select signals */
 	wire IOCS, IOPWCS, IACS;
 	wire ROMCS, ROMCS4X;
-	wire RAMCS, RAMCS0X;
+	wire RAMCS, RAMCS0X, SndRAMCSWR;
 	CS cs(
 		/* MC68HC000 interface */
 		A_FSB[23:08], FCLK, nRESin, nWE_FSB,
@@ -68,7 +68,7 @@ module WarpSE(
 		/* Device select outputs */
 		IOCS, IOPWCS, IACS,
 		ROMCS, ROMCS4X,
-		RAMCS, RAMCS0X);
+		RAMCS, RAMCS0X, SndRAMCSWR);
 
 	wire RAMReady;
 	RAM ram(
@@ -128,6 +128,7 @@ module WarpSE(
 		IORDREQ, IOWRREQ, IOL0, IOU0,
 		IOACT, IODONE, IOBERR);
 
+	wire QoSReady;
 	CNT cnt(
 		/* FSB clock and E clock inputs */
 		FCLK, E,
@@ -136,7 +137,9 @@ module WarpSE(
 		/* Reset, button */
 		nRESout, nIPL2, 
 		/* Mac PDS bus master control outputs */
-		AoutOE, nBR_IOB);
+		AoutOE, nBR_IOB,
+		/* Sound QoS */
+		BACT, SndRAMCSWR, QoSReady);
 	
 	FSB fsb(
 		/* MC68HC000 interface */
@@ -148,6 +151,8 @@ module WarpSE(
 		RAMCS0X, RAMReady,
 		IOPWCS, IOPWReady, IONPReady,
 		/* Interrupt acknowledge select */
-		IACS);
+		IACS,
+		/* Sound QoS */
+		QoSReady);
 
 endmodule