diff --git a/cpld/CNT.v b/cpld/CNT.v index ffd1a64..ae9a092 100644 --- a/cpld/CNT.v +++ b/cpld/CNT.v @@ -1,107 +1,121 @@ module CNT( - /* C16M clock */ - input C16M, + /* C8M clock input */ + input C8M, /* FSB clock and bus active signal */ - input FCLK, input BACT, + input FCLK, input LBACT, /* Refresh request */ output reg RefReq, output RefUrgent, - /* BERR and QoS speed limit output */ - output reg BERRTimeout, output reg QoSGate, + /* BERR output */ + output reg BERRTimeout, /* Reset, switch, button */ input [3:1] SW, input nRESin, output reg nRESout, input nIPL2, + /* Mac PDS bus master control outputs */ + output reg AoutOE, output nAoutOE, output nBR_IOB, /* Configuration outputs */ - output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN); + output reg WarpEnable, output reg FastROMEN, output C20MEN, output C25MEN); - /* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */ - reg [7:0] Timer = 0; - wire TimerTC = Timer[7:5]==3'b111; - always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1; + /* Timer counts from 0 to 1100000 (96) -- 97 states == 12.382 us */ + reg [6:0] Timer = 0; + wire TimerTC = Timer[6:5]==2'b11; + always @(posedge C8M) Timer <= TimerTC ? 0 : Timer+1; - /* Refresh timer outputs - * ___ ______________________________________ - * RefReq |___________| |__________ - * ___ ^ Timer==0 ^ Timer==17 _____________^ Timer==0 - * RefUrg |____________________________________| |__________ - * ^ Timer==0 ^ Timer==128 ^ Timer==0 + /* Refresh timer sequence + * | Timer | RefReq | RefUrgent | + * |----------------------------| + * | 0 | 0 | 0 | + * | 1 | 0 | 0 | + * | 2 | 0 | 0 | + * | 3 | 0 | 0 | + * | 4 | 0 | 0 | + * | 5 | 0 | 0 | + * | 6 | 0 | 0 | + * | 7 | 0 | 0 | + * | 8 | 0 | 0 | + * | 9 | 1 | 0 | + * | 10 | 1 | 0 | + * | 11 | 1 | 0 | + * | ... | 1 | 0 | + * | 62 | 1 | 0 | + * | 63 | 1 | 0 | + * | 64 | 1 | 1 | + * | 65 | 1 | 1 | + * | 66 | 1 | 1 | + * | ... | 1 | 1 | + * | 93 | 1 | 1 | + * | 94 | 1 | 1 | + * | 95 | 1 | 1 | + * | 96 | 1 | 1 | + * back to timer==0 */ - assign RefUrgent = Timer[7]; - always @(posedge C16M) begin - if (Timer[4]) RefREQ <= 1; + assign RefUrgent = Timer[6]; + always @(posedge C8M) begin + if (Timer[3]) RefREQ <= 1; else if (TimerTC) RefREQ <= 0; end - /* NBACT - "Narrow BACT" in FCLK clock domain */ - reg [1:0] BACTCnt = 0; - reg NBACT; - always @(posedge FCLK) begin - if (!BACT) begin - BACTCnt <= 0; - NBACT <= 0; - end else begin - BACTCnt <= BACTCnt+1; - if (BACTCnt==2'b11 && BACT) NBACT <= 1; - end - end + /* LBACTr - LBACT synchronized to C16M clock domain */ + reg LBACTr; + always @(posedge C8M) LBACTr <= LBACT; - /* NBACTr - NBACT synchronized to C16M clock domain */ - reg NBACTr; - always @(posedge C16M) NBACTr <= NBACT; - - /* BERR generation in C16M clock domain */ + /* BERR generation in C8M clock domain */ reg BERRArm = 0; reg BERRTimeout = 0; - always @(posedge C16M) begin - if (NBACTr && TimerTC) begin + always @(posedge C8M) begin + if (LBACTr && TimerTC) begin BERRArm <= 1; if (BERRArm) BERRTimeout <= 1; - end else if (!NBACTr) begin + end else if (!LBACTr) begin BERRArm <= 0; BERRTimeout <= 0; end end - /* Sound QoS counter */ - reg [13:0] SC; // Sound counter - always @(posedge C16M) begin - if (TimerTC) SC <= SC+1; // SC increment - end - - /* IPL2 registration */ - reg nIPL2r, nRESr; - always @(negedge C16M) begin - nIPL2r <= nIPL2; - nRESr <= nRES; + /* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */ + reg [14:0] LTimer; // Long timer + wire LTimerTC <= LTimer[14]; + always @(posedge C8M) begin + if (LTimerTC) LTimer <= 0; + else LTimer <= LTimer+1; end /* Startup sequence control */ reg [1:0] PORS = 0; - always @(posedge C16M) begin + reg Disable = 0; + reg BR_IOB = 0; assign nBR_IOB <= !BR_IOB; + assign nAoutOE <= !AoutOE; + always @(posedge C8M) begin case (PORS) 0: begin - nRESout <= !nRESr; - if (nRESr) PORS <= 1; + AoutOE <= 0; // Tristate PDS address and control + nRESout <= 0; // Hold reset low + Disable <= 0; + if (LTimerTC) PORS <= 1; end 1: begin - nRESout <= 0; - if (TimerTC && SC[13:0]==14'h3FFF && nIPL2r) PORS <= 2; + AoutOE <= 0; // Tristate PDS address and control + nRESout <= 0; // Hold reset low + Disable <= Disable | !nIPL2; // No need to synchronize /IPL2 + if (!IPL2r && LTimerTC) begin + BR_IOB <= !Disable; + PORS <= 2; + end end 2: begin - nRESout <= 0; - if (TimerTC && SC[13:0]==14'h3FFF) PORS <= 3; + AoutOE <= 0; // Tristate PDS address and control + nRESout <= 0; // Hold reset low + if (LTimerTC) PORS <= 3; end 3: begin - nRESout <= 1; + AoutOE <= BR_IOB; + // Wait until LTimerTC to release reset + if (LTimerTC) nRESout <= 1; + else nRESout = 0; + PORS <= 3; end endcase end - /* Accelerator enable/disable control */ - always @(posedge CLK) begin - if (PORS==0) begin - if (nRESr) nBR_IOB <= nIPL2r; - else nBR_IOB <= 1; - end - end - // Enable both oscillators... only mount one assign C20MEN = 1; assign C25MEN = 1; + // Enable fast ROM + assign FastROMEN = 1; endmodule diff --git a/cpld/FSB.v b/cpld/FSB.v index 60a71d0..48df912 100644 --- a/cpld/FSB.v +++ b/cpld/FSB.v @@ -2,7 +2,7 @@ module FSB( /* MC68HC000 interface */ input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR, /* AS cycle detection */ - output BACT, + output BACT, output LBACT, /* Ready inputs */ input Ready0, input Ready1, input Ready2, /* BERR inputs */ @@ -13,7 +13,20 @@ module FSB( /* AS cycle detection */ reg ASrf = 0; always @(negedge FCLK) begin ASrf <= ~nAS; end - assign BACT = ~nAS || ASrf; + assign BACT = ~nAS || ASrf; // BACT - bus active + + /* LBACT - "Long BACT" */ + reg [1:0] BACTCnt = 0; + reg LBACT; + always @(posedge FCLK) begin + if (!BACT) begin + BACTCnt <= 0; + LBACT <= 0; + end else begin + BACTCnt <= BACTCnt+1; + if (BACTCnt==2'b11 && BACT) LBACT <= 1; + end + end /* Ready generation and bypass */ reg Ready0r, Ready1r, Ready2r; diff --git a/cpld/IOBM.v b/cpld/IOBM.v index 1e8fc64..b17a272 100644 --- a/cpld/IOBM.v +++ b/cpld/IOBM.v @@ -4,7 +4,7 @@ module IOBM( output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA, input nASin, input nBG, input nDTACK, input nVPA, input nBERR, input nRES, /* PDS address and data latch control */ - output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE, + input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE, /* IO bus slave port interface */ output reg IOACT, output reg IOBERR, input IOREQ, input IOLDS, input IOUDS, input IOWE); @@ -107,11 +107,11 @@ module IOBM( end /* PDS address and data latch control */ - assign nAoutOE = !BG; always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end + reg DoutOE = 0; assign nDoutOE <= !(AoutOE && DoutOE); always @(posedge C16M) begin - nDoutOE <= ~(IOWE && (IOS==1 || IOS==2 || IOS==3 || - IOS==4 || IOS==5 || IOS==6)); + DoutOE <= IOWE && (IOS==1 || IOS==2 || IOS==3 || + IOS==4 || IOS==5 || IOS==6); end /* AS, DS control */ diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v index 8b1de78..75b89bb 100644 --- a/cpld/WarpSE.v +++ b/cpld/WarpSE.v @@ -47,6 +47,7 @@ module WarpSE( /* AS cycle detection */ wire BACT; + wire LBACT; /* Refresh request/ack signals */ wire RefReq, RefUrgent; @@ -112,31 +113,34 @@ module WarpSE( nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout, nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin, /* PDS address and data latch control */ - nAoutOE, nDoutOE, ALE0M, nDinLE, + AoutOE, nDoutOE, ALE0M, nDinLE, /* IO bus slave port interface */ IOACT, IOBERR, IOREQ, IOL0, IOU0, IORW0); - wire BERRTimeout, QoSReady; + wire BERRTimeout; + wire AoutOE; CNT cnt( - /* C16M clock */ - C16M, - /* FSB clock and bus active signal */ - FCLK, BACT, + /* C8M clock */ + C8M, + /* FSB bus active signals */ + BACT, LBACT, /* Refresh request */ RefReq, RefUrgent, /* BERR and QoS speed limit output */ - BERRTimeout, QoSReady, + BERRTimeout, /* Reset, switch, button */ SW[3:1], nRESin, nRESout, nIPL2, + /* Mac PDS bus master control outputs */ + nAoutOE, AoutOE, nBR_IOB, /* Configuration outputs */ - nBR_IOB, FastROMEN, C20MEN, C25MEN); + FastROMEN, C20MEN, C25MEN); FSB fsb( /* MC68HC000 interface */ CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB, /* AS cycle detection */ - BACT, + BACT, LBACT, /* Ready and IA inputs */ Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady), /* BERR inputs */