From ffad08ffb5035c710df6e6f10fe62f5269d861f4 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 9 Oct 2024 04:15:23 -0400 Subject: [PATCH] Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD. --- cpld/IOBS.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpld/IOBS.v b/cpld/IOBS.v index 58a15f8..334c7c4 100644 --- a/cpld/IOBS.v +++ b/cpld/IOBS.v @@ -51,7 +51,7 @@ module IOBS( // I/O selected, and FIFO secondary level empty if (BACT && IOPWCS && !ALE1 && !Sent && TS!=0) begin // Latch R/W now but latch address and LDS/UDS next cycle - IORW1 <= nWE || !IORealCS; + IORW1 <= nWE;// || !IORealCS; Load1 <= 1; end else Load1 <= 0; end @@ -87,7 +87,7 @@ module IOBS( IOL0 <= IOL1; IOU0 <= IOU1; end else begin // FSB request - IORW <= nWE || !IORealCS; + IORW <= nWE;// || !IORealCS; IOL0 <= !nLDS; IOU0 <= !nUDS; end