18 Commits

Author	SHA1	Message	Date
Zane Kaminski	2a69312ba4	Fix /VMA setup time before E clock	2024-10-06 23:07:36 -04:00
Zane Kaminski	8767a92544	PDS bridge refactor	2024-10-03 11:48:59 -04:00
Zane Kaminski	10ebdd43ba	Back to "old robust"	2024-10-03 05:51:10 -04:00
Zane Kaminski	b119c460ca	simplifying CPLD functions, add IOB RW, slow SCSI back down	2024-09-30 23:36:18 -04:00
Zane Kaminski	4703958dd6	New more cycle-accurate slowdown	2024-09-29 03:29:49 -04:00
Zane Kaminski	804e84d1e2	Works with new Ready. RAM still untested	2023-04-07 00:41:16 -04:00
Zane Kaminski	a60c54fb6c	Much better RAM and FSB controller draft	2023-04-06 23:11:11 -04:00
Zane Kaminski	1f60dbe361	Works well but fast RAM disabled	2023-04-01 04:46:47 -04:00
Zane Kaminski	34259dd51c	Fixed cycle termination signal synchronization in IOBM	2023-03-31 23:18:22 -04:00
Zane Kaminski	8443707339	idk	2023-03-26 04:33:59 -04:00
Zane Kaminski	d126c6b0cb	Redo CNT timers	2023-03-25 03:49:44 -04:00
Zane Kaminski	a2fc4dc4de	Better	2023-03-20 01:13:11 -04:00
Zane Kaminski	fb6b6debcc	Improved a lot of stuff	2023-03-20 00:53:10 -04:00
Zane Kaminski	f9c184ea9f	POR changes	2022-09-11 17:15:53 -04:00
Zane Kaminski	a91c6c4ffb	New stuff	2022-09-03 21:32:05 -04:00
Zane Kaminski	1893b9b835	Prototype	2022-03-27 23:45:53 -04:00
Zane Kaminski	5b659cc42a	idk	2022-01-16 10:56:37 -05:00
Zane Kaminski	6986fad3ae	add from other repo	2021-10-29 06:04:59 -04:00