Release 14.7 - xst P.20131013 (nt) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.80 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.84 secs --> Reading design: WarpSE.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "WarpSE.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "WarpSE" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : WarpSE Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 2 Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "../RAM.v" in library work Compiling verilog file "../IOBS.v" in library work Module compiled Compiling verilog file "../IOBM.v" in library work Module compiled Compiling verilog file "../FSB.v" in library work Module compiled Compiling verilog file "../CS.v" in library work Module compiled Compiling verilog file "../CNT.v" in library work Module compiled Compiling verilog file "../CLK.v" in library work Module compiled Compiling verilog file "../WarpSE.v" in library work Module compiled Module compiled No errors in compilation Analysis of file <"WarpSE.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. Synthesizing Unit . Related source file is "../CLK.v". WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:1305 - Output > is never assigned. Tied to value 0. Found 2-bit register for signal >. Found 1-bit register for signal . Found 2-bit adder for signal <$add0000> created at line 6. Summary: inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "../CS.v". Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../RAM.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 2 | | Outputs | 4 | | Clock | CLK (rising_edge) | | Clock enable | RS$cmp_eq0000 (positive) | | Power Up State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 21 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../IOBS.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 10 | | Inputs | 5 | | Outputs | 5 | | Clock | CLK (rising_edge) | | Power Up State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 9 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../IOBM.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 16 | | Inputs | 7 | | Outputs | 8 | | Clock | C16M (rising_edge) | | Power Up State | 000 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 5-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 22 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../CNT.v". Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is "../FSB.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../WarpSE.v". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 7 D-type flip-flop(s). inferred 4 Tristate(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 2-bit adder : 1 # Counters : 2 5-bit up counter : 1 8-bit up counter : 1 # Registers : 83 1-bit register : 83 # Tristates : 4 1-bit tristate buffer : 4 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ------------------- State | Encoding ------------------- 000 | 000 001 | 001 010 | 011 011 | 010 100 | 110 101 | 111 110 | 101 111 | 100 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with johnson encoding. ------------------- State | Encoding ------------------- 00 | 00 11 | 01 10 | 11 01 | 10 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with compact encoding. ------------------- State | Encoding ------------------- 00 | 10 01 | 00 11 | 11 10 | 01 ------------------- WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. You should achieve better results by setting this init to 1. WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable. You should achieve better results by setting this init to 1. ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 3 # Adders/Subtractors : 1 2-bit adder : 1 # Counters : 2 5-bit up counter : 1 8-bit up counter : 1 # Registers : 65 Flip-Flops : 65 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1426 - The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE. You should achieve better results by setting this init to 1. WARNING:Xst:1426 - The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE. You should achieve better results by setting this init to 1. Optimizing unit ... implementation constraint: INIT=r : RESr0 implementation constraint: INIT=r : RESr1 implementation constraint: INIT=r : RESr2 implementation constraint: INIT=r : IPL2r0 implementation constraint: INIT=r : IPL2r1 implementation constraint: INIT=r : Disable implementation constraint: INIT=r : RESDone implementation constraint: INIT=r : ram/Once3 implementation constraint: INIT=r : ram/Once1 implementation constraint: INIT=r : iobs/PS_FSM_FFd1 implementation constraint: INIT=r : iobs/IOACTr implementation constraint: INIT=r : iobs/Once implementation constraint: INIT=r : cs/nOverlay0 implementation constraint: INIT=r : cs/nOverlay1 implementation constraint: INIT=r : iobm/IOREQr implementation constraint: INIT=r : iobs/PS_FSM_FFd2 implementation constraint: INIT=r : iobm/IOS_FSM_FFd2 implementation constraint: INIT=r : iobm/IOS_FSM_FFd3 implementation constraint: INIT=r : iobm/ETACK implementation constraint: INIT=r : iobm/BGr0 implementation constraint: INIT=r : iobm/BGr1 implementation constraint: INIT=r : iobm/BG implementation constraint: INIT=s : ram/RS_FSM_FFd1 implementation constraint: INIT=r : ram/RS_FSM_FFd2 implementation constraint: INIT=r : cnt/RefCnt_0 implementation constraint: INIT=r : cnt/RefCnt_1 implementation constraint: INIT=r : cnt/RefCnt_2 implementation constraint: INIT=r : cnt/RefCnt_3 implementation constraint: INIT=r : cnt/RefCnt_4 implementation constraint: INIT=r : cnt/RefCnt_5 implementation constraint: INIT=r : cnt/RefCnt_6 implementation constraint: INIT=r : cnt/RefCnt_7 implementation constraint: INIT=r : iobm/IOS_FSM_FFd1 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : WarpSE.ngr Top Level Output File Name : WarpSE Output Format : NGC Optimization Goal : Speed Keep Hierarchy : No Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 79 Cell Usage : # BELS : 631 # AND2 : 180 # AND3 : 29 # AND4 : 13 # AND5 : 1 # AND6 : 1 # AND7 : 1 # AND8 : 3 # GND : 1 # INV : 266 # OR2 : 109 # OR3 : 9 # OR4 : 3 # VCC : 1 # XOR2 : 14 # FlipFlops/Latches : 103 # FD : 72 # FDCE : 31 # Tri-States : 1 # BUFE : 1 # IO Buffers : 78 # IBUF : 39 # OBUF : 35 # OBUFE : 4 ========================================================================= Total REAL time to Xst completion: 23.00 secs Total CPU time to Xst completion: 22.87 secs --> Total memory usage is 205652 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 10 ( 0 filtered) Number of infos : 1 ( 0 filtered)