Timing Report

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Design Name WarpSE
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sun Jul 16 02:14:21 2023
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 20.100 ns.
Max. Clock Frequency (fSYSTEM) 49.751 MHz.
Limited by Cycle Time for FCLK
Clock to Setup (tCYC) 20.100 ns.
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 16.600 ns.
Clock Pad to Output Pad Delay (tCO) 14.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 20.1 643 643
AUTO_TS_P2P 0.0 14.5 82 82
AUTO_TS_P2F 0.0 18.4 219 219
AUTO_TS_F2P 0.0 12.7 45 45


Constraint: TS1000

Description: PERIOD:PERIOD_FCLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_C16M:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_C8M:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
cnt/IS_FSM_FFd1.Q to cnt/LTimer<0>.D 0.000 20.100 -20.100
cnt/IS_FSM_FFd2.Q to cnt/LTimer<0>.D 0.000 20.100 -20.100
fsb/ASrf.Q to cnt/LTimer<0>.D 0.000 20.100 -20.100


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
FCLK to RA<11> 0.000 14.500 -14.500
FCLK to nAS_IOB 0.000 14.500 -14.500
FCLK to nDinOE 0.000 14.500 -14.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A_FSB<10> to cnt/LTimer<0>.D 0.000 18.400 -18.400
A_FSB<11> to cnt/LTimer<0>.D 0.000 18.400 -18.400
A_FSB<12> to cnt/LTimer<0>.D 0.000 18.400 -18.400


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
cs/nOverlay.Q to nDinOE 0.000 12.700 -12.700
nAoutOE.Q to nAS_IOB 0.000 12.700 -12.700
nAoutOE.Q to nLDS_IOB 0.000 12.700 -12.700



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
FCLK 49.751 Limited by Cycle Time for FCLK
C16M 90.909 Limited by Cycle Time for C16M
C8M 100.000 Limited by Cycle Time for C8M

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FCLK
Source Pad Setup to clk (edge) Hold to clk (edge)
A_FSB<10> 16.600 0.000
A_FSB<11> 16.600 0.000
A_FSB<12> 16.600 0.000
A_FSB<13> 16.600 0.000
A_FSB<14> 16.600 0.000
A_FSB<15> 16.600 0.000
A_FSB<16> 16.600 0.000
A_FSB<17> 16.600 0.000
A_FSB<18> 16.600 0.000
A_FSB<19> 16.600 0.000
A_FSB<20> 16.600 0.000
A_FSB<21> 16.600 0.000
A_FSB<22> 16.600 0.000
A_FSB<23> 16.600 0.000
A_FSB<8> 16.600 0.000
A_FSB<9> 16.600 0.000
C8M 6.500 0.000
E 6.500 0.000
nAS_FSB 16.600 0.000
nIPL2 6.500 0.000
nLDS_FSB 6.500 0.000
nRES 6.500 0.000
nUDS_FSB 6.500 0.000
nWE_FSB 16.600 0.000

Setup/Hold Times for Clock C16M
Source Pad Setup to clk (edge) Hold to clk (edge)
C8M 6.500 0.000

Setup/Hold Times for Clock C8M
Source Pad Setup to clk (edge) Hold to clk (edge)
E 6.500 0.000
nBERR_IOB 6.500 0.000
nDTACK_IOB 6.500 0.000
nRES 6.500 0.000
nVPA_IOB 6.500 0.000


Clock to Pad Timing

Clock FCLK to Pad
Destination Pad Clock (edge) to Pad
RA<11> 14.500
nAS_IOB 14.500
nDinOE 14.500
nLDS_IOB 14.500
nRAMUWE 14.500
nRES 14.500
nUDS_IOB 14.500
nVMA_IOB 14.500
RA<0> 13.500
RA<10> 13.500
RA<1> 13.500
RA<2> 13.500
RA<3> 13.500
RA<4> 13.500
RA<5> 13.500
RA<6> 13.500
RA<7> 13.500
RA<8> 13.500
RA<9> 13.500
nADoutLE0 13.500
nDoutOE 13.500
nRAMLWE 13.500
nRAS 13.500
nROMCS 13.500
nADoutLE1 5.800
nAoutOE 5.800
nBERR_FSB 5.800
nBR_IOB 5.800
nCAS 5.800
nDTACK_FSB 5.800
nOE 5.800
nVPA_FSB 5.800

Clock C16M to Pad
Destination Pad Clock (edge) to Pad
nADoutLE0 13.500
nDoutOE 13.500
nAS_IOB 5.800
nDinLE 5.800
nLDS_IOB 5.800
nUDS_IOB 5.800

Clock C8M to Pad
Destination Pad Clock (edge) to Pad
nVMA_IOB 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock FCLK
Source Destination Delay
cnt/IS_FSM_FFd1.Q cnt/LTimer<0>.D 20.100
cnt/IS_FSM_FFd2.Q cnt/LTimer<0>.D 20.100
fsb/ASrf.Q cnt/LTimer<0>.D 20.100
cnt/IS_FSM_FFd1.Q cnt/LTimer<1>.D 19.700
cnt/IS_FSM_FFd2.Q cnt/LTimer<1>.D 19.700
fsb/ASrf.Q cnt/LTimer<1>.D 19.700
cnt/Er<0>.Q cnt/LTimer<0>.D 19.100
cnt/Er<1>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<0>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<10>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<11>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<1>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<2>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<3>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<4>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<5>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<6>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<7>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<8>.Q cnt/LTimer<0>.D 19.100
cnt/LTimer<9>.Q cnt/LTimer<0>.D 19.100
cnt/TimerTC.Q cnt/LTimer<0>.D 19.100
cnt/Er<0>.Q cnt/LTimer<1>.D 18.700
cnt/Er<1>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<0>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<10>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<11>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<1>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<2>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<3>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<4>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<5>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<6>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<7>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<8>.Q cnt/LTimer<1>.D 18.700
cnt/LTimer<9>.Q cnt/LTimer<1>.D 18.700
cnt/TimerTC.Q cnt/LTimer<1>.D 18.700
IONPReady.Q nDTACK_FSB.D 11.400
cs/nOverlay.Q IOL0.D 11.400
cs/nOverlay.Q IOU0.D 11.400
cs/nOverlay.Q iobs/Sent.D 11.400
fsb/ASrf.Q iobs/Sent.D 11.400
iobs/Sent.Q iobs/Sent.D 11.400
iobs/Sent.Q nDTACK_FSB.D 11.400
iobs/TS_FSM_FFd1.Q iobs/Sent.D 11.400
iobs/TS_FSM_FFd2.Q IOL0.D 11.400
iobs/TS_FSM_FFd2.Q IOU0.D 11.400
iobs/TS_FSM_FFd2.Q iobs/Sent.D 11.400
nADoutLE1.Q IOL0.D 11.400
nADoutLE1.Q IOU0.D 11.400
nADoutLE1.Q iobs/Sent.D 11.400
nADoutLE1.Q nDTACK_FSB.D 11.400
BACTr.Q RAMReady.D 11.000
BACTr.Q nCAS.D 11.000
BACTr.Q nOE.D 11.000
BACTr.Q ram/RASEN.D 11.000
BACTr.Q ram/RASrr.D 11.000
BACTr.Q ram/RS_FSM_FFd7.D 11.000
BACTr.Q ram/RS_FSM_FFd8.D 11.000
IOL0.Q IOL0.D 11.000
IONPReady.Q nVPA_FSB.D 11.000
IOU0.Q IOU0.D 11.000
QoSReady.Q nVPA_FSB.D 11.000
RAMReady.Q nDTACK_FSB.D 11.000
RefReq.Q RAMReady.D 11.000
RefReq.Q nCAS.D 11.000
RefReq.Q ram/RASEN.D 11.000
RefReq.Q ram/RASrr.D 11.000
RefReq.Q ram/RS_FSM_FFd7.D 11.000
RefReq.Q ram/RS_FSM_FFd8.D 11.000
RefUrg.Q RAMReady.D 11.000
RefUrg.Q nCAS.D 11.000
RefUrg.Q ram/RASEN.D 11.000
RefUrg.Q ram/RASrr.D 11.000
RefUrg.Q ram/RS_FSM_FFd8.D 11.000
WS.Q cnt/Credits<0>.D 11.000
WS.Q cnt/Credits<1>.D 11.000
WS.Q cnt/Credits<2>.D 11.000
WS.Q cnt/Credits<3>.D 11.000
WS.Q cnt/Credits<4>.D 11.000
WS.Q cnt/Credits<5>.D 11.000
WS.Q cnt/Credits<6>.D 11.000
WS.Q cnt/Credits<7>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<0>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<1>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<2>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<3>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<4>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<5>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<6>.D 11.000
cnt/C8Mr<0>.Q cnt/Credits<7>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<0>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<1>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<2>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<3>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<4>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<5>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<6>.D 11.000
cnt/C8Mr<1>.Q cnt/Credits<7>.D 11.000
cnt/Credits<0>.Q cnt/Credits<0>.D 11.000
cnt/Credits<0>.Q cnt/Credits<1>.D 11.000
cnt/Credits<0>.Q cnt/Credits<2>.D 11.000
cnt/Credits<0>.Q cnt/Credits<3>.D 11.000
cnt/Credits<0>.Q cnt/Credits<4>.D 11.000
cnt/Credits<0>.Q cnt/Credits<5>.D 11.000
cnt/Credits<0>.Q cnt/Credits<6>.D 11.000
cnt/Credits<0>.Q cnt/Credits<7>.D 11.000
cnt/Credits<1>.Q cnt/Credits<2>.D 11.000
cnt/Credits<1>.Q cnt/Credits<3>.D 11.000
cnt/Credits<1>.Q cnt/Credits<4>.D 11.000
cnt/Credits<1>.Q cnt/Credits<5>.D 11.000
cnt/Credits<1>.Q cnt/Credits<6>.D 11.000
cnt/Credits<1>.Q cnt/Credits<7>.D 11.000
cnt/Credits<2>.Q cnt/Credits<3>.D 11.000
cnt/Credits<2>.Q cnt/Credits<4>.D 11.000
cnt/Credits<2>.Q cnt/Credits<5>.D 11.000
cnt/Credits<2>.Q cnt/Credits<6>.D 11.000
cnt/Credits<2>.Q cnt/Credits<7>.D 11.000
cnt/Credits<3>.Q cnt/Credits<4>.D 11.000
cnt/Credits<3>.Q cnt/Credits<5>.D 11.000
cnt/Credits<3>.Q cnt/Credits<6>.D 11.000
cnt/Credits<3>.Q cnt/Credits<7>.D 11.000
cnt/Credits<4>.Q cnt/Credits<5>.D 11.000
cnt/Credits<4>.Q cnt/Credits<6>.D 11.000
cnt/Credits<4>.Q cnt/Credits<7>.D 11.000
cnt/Credits<5>.Q cnt/Credits<6>.D 11.000
cnt/Credits<5>.Q cnt/Credits<7>.D 11.000
cnt/Credits<6>.Q cnt/Credits<7>.D 11.000
cnt/Credits<7>.Q QoSReady.D 11.000
cnt/Er<0>.Q cnt/LTimer<11>.D 11.000
cnt/Er<0>.Q cnt/Timer<1>.D 11.000
cnt/Er<1>.Q cnt/LTimer<11>.D 11.000
cnt/Er<1>.Q cnt/Timer<1>.D 11.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<11>.D 11.000
cnt/IS_FSM_FFd1.Q nAoutOE.D 11.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<11>.D 11.000
cnt/IS_FSM_FFd2.Q nAoutOE.D 11.000
cnt/LTimer<0>.Q QoSReady.D 11.000
cnt/LTimer<0>.Q cnt/Credits<1>.D 11.000
cnt/LTimer<0>.Q cnt/Credits<2>.D 11.000
cnt/LTimer<0>.Q cnt/Credits<3>.D 11.000
cnt/LTimer<0>.Q cnt/Credits<4>.D 11.000
cnt/LTimer<0>.Q cnt/Credits<5>.D 11.000
cnt/LTimer<0>.Q cnt/Credits<6>.D 11.000
cnt/LTimer<0>.Q cnt/Credits<7>.D 11.000
cnt/LTimer<0>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<0>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<10>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<10>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<11>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<11>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<1>.Q QoSReady.D 11.000
cnt/LTimer<1>.Q cnt/Credits<1>.D 11.000
cnt/LTimer<1>.Q cnt/Credits<2>.D 11.000
cnt/LTimer<1>.Q cnt/Credits<3>.D 11.000
cnt/LTimer<1>.Q cnt/Credits<4>.D 11.000
cnt/LTimer<1>.Q cnt/Credits<5>.D 11.000
cnt/LTimer<1>.Q cnt/Credits<6>.D 11.000
cnt/LTimer<1>.Q cnt/Credits<7>.D 11.000
cnt/LTimer<1>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<1>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<2>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<2>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<3>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<3>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<4>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<4>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<5>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<5>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<6>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<6>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<7>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<7>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<8>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<8>.Q cnt/LTimerTC.D 11.000
cnt/LTimer<9>.Q cnt/LTimer<11>.D 11.000
cnt/LTimer<9>.Q cnt/LTimerTC.D 11.000
cnt/Timer<0>.Q cnt/Timer<1>.D 11.000
cnt/Timer<1>.Q cnt/Timer<1>.D 11.000
cnt/TimerTC.Q cnt/LTimer<11>.D 11.000
cnt/TimerTC.Q cnt/Timer<1>.D 11.000
cs/nOverlay.Q IORDREQ.D 11.000
cs/nOverlay.Q IOWRREQ.D 11.000
cs/nOverlay.Q iobs/TS_FSM_FFd2.D 11.000
cs/nOverlay.Q ram/RASrr.D 11.000
cs/nOverlay.Q ram/RS_FSM_FFd8.D 11.000
fsb/ASrf.Q IOL0.D 11.000
fsb/ASrf.Q IONPReady.D 11.000
fsb/ASrf.Q IORDREQ.D 11.000
fsb/ASrf.Q IOU0.D 11.000
fsb/ASrf.Q IOWRREQ.D 11.000
fsb/ASrf.Q QoSReady.D 11.000
fsb/ASrf.Q RAMReady.D 11.000
fsb/ASrf.Q iobs/IORW1.D 11.000
fsb/ASrf.Q iobs/Load1.D 11.000
fsb/ASrf.Q nCAS.D 11.000
fsb/ASrf.Q nOE.D 11.000
fsb/ASrf.Q nVPA_FSB.D 11.000
fsb/ASrf.Q ram/RASEN.D 11.000
fsb/ASrf.Q ram/RASrr.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd7.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd8.D 11.000
iobs/IOL1.Q IOL0.D 11.000
iobs/IORW1.Q IORDREQ.D 11.000
iobs/IORW1.Q iobs/IORW1.D 11.000
iobs/IOU1.Q IOU0.D 11.000
iobs/Sent.Q IOWRREQ.D 11.000
iobs/Sent.Q iobs/IORW1.D 11.000
iobs/Sent.Q iobs/Load1.D 11.000
iobs/TS_FSM_FFd1.Q IOWRREQ.D 11.000
iobs/TS_FSM_FFd1.Q iobs/IORW1.D 11.000
iobs/TS_FSM_FFd1.Q iobs/Load1.D 11.000
iobs/TS_FSM_FFd2.Q IORDREQ.D 11.000
iobs/TS_FSM_FFd2.Q IOWRREQ.D 11.000
iobs/TS_FSM_FFd2.Q iobs/IORW1.D 11.000
iobs/TS_FSM_FFd2.Q iobs/TS_FSM_FFd2.D 11.000
nADoutLE1.Q IORDREQ.D 11.000
nADoutLE1.Q IOWRREQ.D 11.000
nADoutLE1.Q iobs/IORW1.D 11.000
nADoutLE1.Q iobs/Load1.D 11.000
nADoutLE1.Q iobs/TS_FSM_FFd2.D 11.000
nAoutOE.Q nAoutOE.D 11.000
nBERR_FSB.Q nBERR_FSB.D 11.000
nBR_IOB.Q nAoutOE.D 11.000
ram/DTACKr.Q nOE.D 11.000
ram/DTACKr.Q ram/RS_FSM_FFd4.D 11.000
ram/RASEN.Q nCAS.D 11.000
ram/RASEN.Q ram/RASrr.D 11.000
ram/RASEN.Q ram/RS_FSM_FFd8.D 11.000
ram/RS_FSM_FFd1.Q RAMReady.D 11.000
ram/RS_FSM_FFd1.Q ram/RASEN.D 11.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd8.D 11.000
ram/RS_FSM_FFd4.Q RAMReady.D 11.000
ram/RS_FSM_FFd4.Q nCAS.D 11.000
ram/RS_FSM_FFd4.Q ram/RASEN.D 11.000
ram/RS_FSM_FFd4.Q ram/RS_FSM_FFd8.D 11.000
ram/RS_FSM_FFd5.Q RAMReady.D 11.000
ram/RS_FSM_FFd5.Q ram/RS_FSM_FFd4.D 11.000
ram/RS_FSM_FFd6.Q RAMReady.D 11.000
ram/RS_FSM_FFd7.Q nCAS.D 11.000
ram/RS_FSM_FFd8.Q nCAS.D 11.000
ram/RS_FSM_FFd8.Q ram/RASrr.D 11.000
ram/RS_FSM_FFd8.Q ram/RS_FSM_FFd7.D 11.000
ram/RS_FSM_FFd8.Q ram/RS_FSM_FFd8.D 11.000
ram/RefDone.Q RAMReady.D 11.000
ram/RefDone.Q nCAS.D 11.000
ram/RefDone.Q ram/RASEN.D 11.000
ram/RefDone.Q ram/RASrr.D 11.000
ram/RefDone.Q ram/RS_FSM_FFd7.D 11.000
ram/RefDone.Q ram/RS_FSM_FFd8.D 11.000
BACTr.Q WS.D 10.000
BACTr.Q fsb/BACTr<1>.D 10.000
IONPReady.Q IONPReady.D 10.000
IORDREQ.Q IORDREQ.D 10.000
IOWRREQ.Q IOWRREQ.D 10.000
QoSReady.Q QoSReady.D 10.000
QoSReady.Q nDTACK_FSB.D 10.000
RefReq.Q ram/RefDone.D 10.000
RefUrg.Q ram/RS_FSM_FFd7.D 10.000
RefUrg.Q ram/RefDone.D 10.000
cnt/C8Mr<0>.Q cnt/C8Mr<1>.D 10.000
cnt/Credits<1>.Q cnt/Credits<1>.D 10.000
cnt/Credits<2>.Q cnt/Credits<2>.D 10.000
cnt/Credits<3>.Q cnt/Credits<3>.D 10.000
cnt/Credits<4>.Q cnt/Credits<4>.D 10.000
cnt/Credits<5>.Q cnt/Credits<5>.D 10.000
cnt/Credits<6>.Q cnt/Credits<6>.D 10.000
cnt/Credits<7>.Q cnt/Credits<7>.D 10.000
cnt/Er<0>.Q RefReq.CE 10.000
cnt/Er<0>.Q RefUrg.CE 10.000
cnt/Er<0>.Q cnt/Er<1>.D 10.000
cnt/Er<0>.Q cnt/IS_FSM_FFd1.D 10.000
cnt/Er<0>.Q cnt/IS_FSM_FFd2.D 10.000
cnt/Er<0>.Q cnt/LTimer<10>.D 10.000
cnt/Er<0>.Q cnt/LTimer<2>.D 10.000
cnt/Er<0>.Q cnt/LTimer<3>.D 10.000
cnt/Er<0>.Q cnt/LTimer<4>.D 10.000
cnt/Er<0>.Q cnt/LTimer<5>.D 10.000
cnt/Er<0>.Q cnt/LTimer<6>.D 10.000
cnt/Er<0>.Q cnt/LTimer<7>.D 10.000
cnt/Er<0>.Q cnt/LTimer<8>.D 10.000
cnt/Er<0>.Q cnt/LTimer<9>.D 10.000
cnt/Er<0>.Q cnt/Timer<0>.CE 10.000
cnt/Er<0>.Q cnt/Timer<0>.D 10.000
cnt/Er<0>.Q cnt/Timer<1>.CE 10.000
cnt/Er<0>.Q cnt/Timer<2>.CE 10.000
cnt/Er<0>.Q cnt/Timer<2>.D 10.000
cnt/Er<0>.Q cnt/Timer<3>.CE 10.000
cnt/Er<0>.Q cnt/Timer<3>.D 10.000
cnt/Er<0>.Q cnt/TimerTC.CE 10.000
cnt/Er<1>.Q RefReq.CE 10.000
cnt/Er<1>.Q RefUrg.CE 10.000
cnt/Er<1>.Q cnt/IS_FSM_FFd1.D 10.000
cnt/Er<1>.Q cnt/IS_FSM_FFd2.D 10.000
cnt/Er<1>.Q cnt/LTimer<10>.D 10.000
cnt/Er<1>.Q cnt/LTimer<2>.D 10.000
cnt/Er<1>.Q cnt/LTimer<3>.D 10.000
cnt/Er<1>.Q cnt/LTimer<4>.D 10.000
cnt/Er<1>.Q cnt/LTimer<5>.D 10.000
cnt/Er<1>.Q cnt/LTimer<6>.D 10.000
cnt/Er<1>.Q cnt/LTimer<7>.D 10.000
cnt/Er<1>.Q cnt/LTimer<8>.D 10.000
cnt/Er<1>.Q cnt/LTimer<9>.D 10.000
cnt/Er<1>.Q cnt/Timer<0>.CE 10.000
cnt/Er<1>.Q cnt/Timer<0>.D 10.000
cnt/Er<1>.Q cnt/Timer<1>.CE 10.000
cnt/Er<1>.Q cnt/Timer<2>.CE 10.000
cnt/Er<1>.Q cnt/Timer<2>.D 10.000
cnt/Er<1>.Q cnt/Timer<3>.CE 10.000
cnt/Er<1>.Q cnt/Timer<3>.D 10.000
cnt/Er<1>.Q cnt/TimerTC.CE 10.000
cnt/IS_FSM_FFd1.Q cnt/IS_FSM_FFd1.D 10.000
cnt/IS_FSM_FFd1.Q cnt/IS_FSM_FFd2.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<10>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<2>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<3>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<4>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<5>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<6>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<7>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<8>.D 10.000
cnt/IS_FSM_FFd1.Q cnt/LTimer<9>.D 10.000
cnt/IS_FSM_FFd1.Q nBR_IOB.D 10.000
cnt/IS_FSM_FFd1.Q nRESout.D 10.000
cnt/IS_FSM_FFd2.Q cnt/IS_FSM_FFd1.D 10.000
cnt/IS_FSM_FFd2.Q cnt/IS_FSM_FFd2.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<10>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<2>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<3>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<4>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<5>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<6>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<7>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<8>.D 10.000
cnt/IS_FSM_FFd2.Q cnt/LTimer<9>.D 10.000
cnt/IS_FSM_FFd2.Q nBR_IOB.D 10.000
cnt/IS_FSM_FFd2.Q nRESout.D 10.000
cnt/LTimer<0>.Q cnt/Credits<0>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<10>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<1>.Q cnt/Credits<0>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<9>.D 10.000
cnt/LTimerTC.Q cnt/IS_FSM_FFd1.D 10.000
cnt/LTimerTC.Q cnt/IS_FSM_FFd2.D 10.000
cnt/Timer<0>.Q RefReq.D 10.000
cnt/Timer<0>.Q cnt/Timer<0>.D 10.000
cnt/Timer<0>.Q cnt/Timer<2>.D 10.000
cnt/Timer<0>.Q cnt/Timer<3>.D 10.000
cnt/Timer<0>.Q cnt/TimerTC.D 10.000
cnt/Timer<1>.Q RefReq.D 10.000
cnt/Timer<1>.Q RefUrg.D 10.000
cnt/Timer<1>.Q cnt/Timer<2>.D 10.000
cnt/Timer<1>.Q cnt/Timer<3>.D 10.000
cnt/Timer<1>.Q cnt/TimerTC.D 10.000
cnt/Timer<2>.Q RefReq.D 10.000
cnt/Timer<2>.Q RefUrg.D 10.000
cnt/Timer<2>.Q cnt/Timer<2>.D 10.000
cnt/Timer<2>.Q cnt/Timer<3>.D 10.000
cnt/Timer<2>.Q cnt/TimerTC.D 10.000
cnt/Timer<3>.Q RefReq.D 10.000
cnt/Timer<3>.Q RefUrg.D 10.000
cnt/Timer<3>.Q cnt/Timer<3>.D 10.000
cnt/Timer<3>.Q cnt/TimerTC.D 10.000
cnt/TimerTC.Q cnt/IS_FSM_FFd1.D 10.000
cnt/TimerTC.Q cnt/IS_FSM_FFd2.D 10.000
cnt/TimerTC.Q cnt/LTimer<10>.D 10.000
cnt/TimerTC.Q cnt/LTimer<2>.D 10.000
cnt/TimerTC.Q cnt/LTimer<3>.D 10.000
cnt/TimerTC.Q cnt/LTimer<4>.D 10.000
cnt/TimerTC.Q cnt/LTimer<5>.D 10.000
cnt/TimerTC.Q cnt/LTimer<6>.D 10.000
cnt/TimerTC.Q cnt/LTimer<7>.D 10.000
cnt/TimerTC.Q cnt/LTimer<8>.D 10.000
cnt/TimerTC.Q cnt/LTimer<9>.D 10.000
cnt/TimerTC.Q cnt/Timer<0>.D 10.000
cnt/TimerTC.Q cnt/Timer<2>.D 10.000
cnt/TimerTC.Q cnt/Timer<3>.D 10.000
cnt/nIPL2r.Q cnt/IS_FSM_FFd1.D 10.000
cnt/nIPL2r.Q nBR_IOB.D 10.000
cs/nOverlay.Q cs/nOverlay.D 10.000
cs/nOverlay.Q ram/RASEL.D 10.000
cs/nOverlay.Q ram/RS_FSM_FFd6.D 10.000
fsb/ASrf.Q BACTr.D 10.000
fsb/ASrf.Q WS.D 10.000
fsb/ASrf.Q cs/nOverlay.D 10.000
fsb/ASrf.Q iobs/TS_FSM_FFd2.D 10.000
fsb/ASrf.Q nBERR_FSB.D 10.000
fsb/ASrf.Q nDTACK_FSB.D 10.000
fsb/ASrf.Q ram/RASEL.D 10.000
fsb/ASrf.Q ram/RS_FSM_FFd6.D 10.000
fsb/BACTr<1>.Q WS.D 10.000
fsb/BACTr<1>.Q fsb/BACTr<2>.D 10.000
fsb/BACTr<2>.Q WS.D 10.000
iobs/Clear1.Q nADoutLE1.D 10.000
iobs/IOACTr.Q IORDREQ.D 10.000
iobs/IOACTr.Q IOWRREQ.D 10.000
iobs/IOACTr.Q iobs/TS_FSM_FFd1.D 10.000
iobs/IOACTr.Q iobs/TS_FSM_FFd2.D 10.000
iobs/IODONEr.Q IONPReady.D 10.000
iobs/IORW1.Q IOWRREQ.D 10.000
iobs/Load1.Q iobs/IOL1.CE 10.000
iobs/Load1.Q iobs/IOU1.CE 10.000
iobs/Load1.Q nADoutLE1.D 10.000
iobs/Sent.Q IOL0.D 10.000
iobs/Sent.Q IONPReady.D 10.000
iobs/Sent.Q IORDREQ.D 10.000
iobs/Sent.Q IOU0.D 10.000
iobs/Sent.Q iobs/TS_FSM_FFd2.D 10.000
iobs/Sent.Q nBERR_FSB.D 10.000
iobs/TS_FSM_FFd1.Q IOL0.D 10.000
iobs/TS_FSM_FFd1.Q IORDREQ.D 10.000
iobs/TS_FSM_FFd1.Q IOU0.D 10.000
iobs/TS_FSM_FFd1.Q iobs/Clear1.D 10.000
iobs/TS_FSM_FFd1.Q iobs/TS_FSM_FFd1.D 10.000
iobs/TS_FSM_FFd1.Q iobs/TS_FSM_FFd2.D 10.000
iobs/TS_FSM_FFd2.Q ALE0S.D 10.000
iobs/TS_FSM_FFd2.Q iobs/Clear1.D 10.000
iobs/TS_FSM_FFd2.Q iobs/Load1.D 10.000
iobs/TS_FSM_FFd2.Q iobs/TS_FSM_FFd1.D 10.000
nADoutLE1.Q nADoutLE1.D 10.000
nBR_IOB.Q nBR_IOB.D 10.000
nDTACK_FSB.Q ram/DTACKr.D 10.000
ram/DTACKr.Q nCAS.D 10.000
ram/DTACKr.Q ram/RS_FSM_FFd5.D 10.000
ram/RASEN.Q RAMReady.D 10.000
ram/RASEN.Q ram/RASEL.D 10.000
ram/RASEN.Q ram/RASEN.D 10.000
ram/RASEN.Q ram/RS_FSM_FFd6.D 10.000
ram/RASEN.Q ram/RS_FSM_FFd7.D 10.000
ram/RS_FSM_FFd1.Q nCAS.D 10.000
ram/RS_FSM_FFd1.Q ram/RefDone.D 10.000
ram/RS_FSM_FFd2.Q nCAS.D 10.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd1.D 10.000
ram/RS_FSM_FFd2.Q ram/RefDone.D 10.000
ram/RS_FSM_FFd3.Q nCAS.D 10.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd2.D 10.000
ram/RS_FSM_FFd3.Q ram/RefDone.D 10.000
ram/RS_FSM_FFd4.Q ram/RASrr.D 10.000
ram/RS_FSM_FFd4.Q ram/RS_FSM_FFd7.D 10.000
ram/RS_FSM_FFd5.Q nCAS.D 10.000
ram/RS_FSM_FFd5.Q ram/RS_FSM_FFd5.D 10.000
ram/RS_FSM_FFd6.Q ram/RASEL.D 10.000
ram/RS_FSM_FFd6.Q ram/RASrf.D 10.000
ram/RS_FSM_FFd6.Q ram/RS_FSM_FFd5.D 10.000
ram/RS_FSM_FFd7.Q ram/RASrr.D 10.000
ram/RS_FSM_FFd7.Q ram/RS_FSM_FFd3.D 10.000
ram/RS_FSM_FFd7.Q ram/RefDone.D 10.000
ram/RS_FSM_FFd8.Q RAMReady.D 10.000
ram/RS_FSM_FFd8.Q ram/RASEL.D 10.000
ram/RS_FSM_FFd8.Q ram/RASEN.D 10.000
ram/RS_FSM_FFd8.Q ram/RS_FSM_FFd6.D 10.000
ram/RefDone.Q ram/RefDone.D 10.000

Clock to Setup for clock C16M
Source Destination Delay
IOACT.Q IOACT.D 11.000
iobm/C8Mr.Q nLDS_IOB.D 11.000
iobm/C8Mr.Q nUDS_IOB.D 11.000
iobm/IORDREQr.Q nLDS_IOB.D 11.000
iobm/IORDREQr.Q nUDS_IOB.D 11.000
iobm/IOS_FSM_FFd1.Q IOACT.D 11.000
iobm/IOS_FSM_FFd2.Q IOACT.D 11.000
iobm/IOS_FSM_FFd3.Q IOACT.D 11.000
iobm/IOS_FSM_FFd7.Q IOACT.D 11.000
iobm/IOS_FSM_FFd7.Q nLDS_IOB.D 11.000
iobm/IOS_FSM_FFd7.Q nUDS_IOB.D 11.000
iobm/IOWRREQr.Q IOACT.D 11.000
ALE0M.Q ALE0M.D 10.000
iobm/C8Mr.Q IOACT.D 10.000
iobm/C8Mr.Q iobm/DoutOE.D 10.000
iobm/C8Mr.Q iobm/IOS0.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/C8Mr.Q nAS_IOB.D 10.000
iobm/DoutOE.Q iobm/DoutOE.D 10.000
iobm/IORDREQr.Q ALE0M.D 10.000
iobm/IORDREQr.Q IOACT.D 10.000
iobm/IORDREQr.Q iobm/IOS0.D 10.000
iobm/IORDREQr.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/IORDREQr.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IORDREQr.Q nAS_IOB.D 10.000
iobm/IOS0.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd1.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IOS_FSM_FFd2.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd3.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd3.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd3.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd4.Q IOACT.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd4.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd4.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd5.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd5.Q IOACT.D 10.000
iobm/IOS_FSM_FFd5.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd5.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd5.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd5.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd5.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd5.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd6.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd6.Q IOACT.D 10.000
iobm/IOS_FSM_FFd6.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd6.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd6.Q iobm/IOS_FSM_FFd5.D 10.000
iobm/IOS_FSM_FFd6.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd6.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd6.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd7.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/IOS0.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IOS_FSM_FFd7.Q nAS_IOB.D 10.000
iobm/IOWRREQr.Q ALE0M.D 10.000
iobm/IOWRREQr.Q iobm/DoutOE.D 10.000
iobm/IOWRREQr.Q iobm/IOS0.D 10.000
iobm/IOWRREQr.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/IOWRREQr.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IOWRREQr.Q nAS_IOB.D 10.000
nLDS_IOB.Q nLDS_IOB.D 10.000
nUDS_IOB.Q nUDS_IOB.D 10.000

Clock to Setup for clock C8M
Source Destination Delay
iobm/ES<0>.Q IODONE.D 10.000
iobm/ES<0>.Q iobm/ES<0>.D 10.000
iobm/ES<0>.Q iobm/ES<1>.D 10.000
iobm/ES<0>.Q iobm/ES<2>.D 10.000
iobm/ES<0>.Q iobm/ES<3>.D 10.000
iobm/ES<0>.Q nVMA_IOB.D 10.000
iobm/ES<1>.Q IODONE.D 10.000
iobm/ES<1>.Q iobm/ES<0>.D 10.000
iobm/ES<1>.Q iobm/ES<1>.D 10.000
iobm/ES<1>.Q iobm/ES<2>.D 10.000
iobm/ES<1>.Q iobm/ES<3>.D 10.000
iobm/ES<1>.Q nVMA_IOB.D 10.000
iobm/ES<2>.Q IODONE.D 10.000
iobm/ES<2>.Q iobm/ES<0>.D 10.000
iobm/ES<2>.Q iobm/ES<1>.D 10.000
iobm/ES<2>.Q iobm/ES<2>.D 10.000
iobm/ES<2>.Q iobm/ES<3>.D 10.000
iobm/ES<2>.Q nVMA_IOB.D 10.000
iobm/ES<3>.Q IODONE.D 10.000
iobm/ES<3>.Q iobm/ES<0>.D 10.000
iobm/ES<3>.Q iobm/ES<1>.D 10.000
iobm/ES<3>.Q iobm/ES<3>.D 10.000
iobm/ES<3>.Q nVMA_IOB.D 10.000
iobm/Er.Q iobm/ES<0>.D 10.000
iobm/Er.Q iobm/ES<1>.D 10.000
iobm/Er.Q iobm/ES<2>.D 10.000
iobm/Er.Q iobm/ES<3>.D 10.000
iobm/VPAr.Q nVMA_IOB.D 10.000
nVMA_IOB.Q IODONE.D 10.000
nVMA_IOB.Q nVMA_IOB.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A_FSB<20> RA<11> 11.000
A_FSB<20> nDinOE 11.000
A_FSB<20> nROMCS 11.000
A_FSB<21> nDinOE 11.000
A_FSB<21> nROMCS 11.000
A_FSB<22> nDinOE 11.000
A_FSB<22> nROMCS 11.000
A_FSB<23> nROMCS 11.000
nAS_FSB nDinOE 11.000
nUDS_FSB nRAMUWE 11.000
nWE_FSB nDinOE 11.000
nWE_FSB nRAMUWE 11.000
A_FSB<10> RA<1> 10.000
A_FSB<11> RA<4> 10.000
A_FSB<12> RA<5> 10.000
A_FSB<13> RA<6> 10.000
A_FSB<14> RA<7> 10.000
A_FSB<15> RA<9> 10.000
A_FSB<16> RA<2> 10.000
A_FSB<17> RA<10> 10.000
A_FSB<18> RA<8> 10.000
A_FSB<19> RA<11> 10.000
A_FSB<19> RA<3> 10.000
A_FSB<1> RA<0> 10.000
A_FSB<20> RA<3> 10.000
A_FSB<21> RA<8> 10.000
A_FSB<22> nRAS 10.000
A_FSB<23> nDinOE 10.000
A_FSB<23> nRAS 10.000
A_FSB<2> RA<1> 10.000
A_FSB<3> RA<4> 10.000
A_FSB<4> RA<5> 10.000
A_FSB<5> RA<6> 10.000
A_FSB<6> RA<7> 10.000
A_FSB<7> RA<10> 10.000
A_FSB<7> RA<2> 10.000
A_FSB<8> RA<9> 10.000
A_FSB<9> RA<0> 10.000
nAS_FSB nRAS 10.000
nAS_FSB nROMWE 10.000
nLDS_FSB nRAMLWE 10.000
nWE_FSB nRAMLWE 10.000
nWE_FSB nROMWE 10.000


Number of paths analyzed: 989
Number of Timing errors: 989
Analysis Completed: Sun Jul 16 02:14:22 2023