CPLD Timing Report (Text)Mon Mar 28 09:30:32 2022
Performance Summary Report
--------------------------
Design: WarpSE
Device: XC95144XL-10-TQ100
Speed File: Version 3.0
Program: Timing Report Generator: version P.20131013
Date: Mon Mar 28 09:28:06 2022
Timing Constraint Summary:
TS_CLK_IOB=PERIOD:CLK_IOB:142.857nS:HIGH:71.428nS N/A
TS_CLK_FSB=PERIOD:CLK_FSB:40.000nS:HIGH:20.000nS Met
TS_CLK2X_IOB=PERIOD:CLK2X_IOB:66.666nS:HIGH:33.333nS Met
Performance Summary:
Pad to Pad (tPD) : 11.0ns (1 macrocell levels)
Pad 'A_FSB<11>' to Pad 'RA<1>'
Clock net 'CLK_IOB' path delays:
Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)
Data signal 'E_IOB' to DFF D input Pin at 'iobm/Er.D'
Clock pad 'CLK_IOB' (GCK)
Minimum Clock Period: 9.0ns
Maximum Internal Clock Speed: 111.1Mhz
(Limited by Clock Pulse Width)
Clock net 'CLK_FSB' path delays:
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
Clock Pad 'CLK_FSB' to Output Pad 'RA<1>' (GCK)
Clock to Setup (tCYC) : 20.1ns (2 macrocell levels)
Clock to Q, net 'cs/nOverlay1.Q' to DFF Setup(D) at 'fsb/VPA.D' (GCK)
Target FF drives output net 'fsb/VPA'
Setup to Clock at the Pad (tSU) : 16.6ns (1 macrocell levels)
Data signal 'A_FSB<23>' to DFF D input Pin at 'fsb/VPA.D'
Clock pad 'CLK_FSB' (GCK)
Minimum Clock Period: 20.1ns
Maximum Internal Clock Speed: 49.7Mhz
(Limited by Cycle Time)
Clock net 'CLK2X_IOB' path delays:
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
Clock Pad 'CLK2X_IOB' to Output Pad 'nVMA_IOB' (GCK)
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
Clock to Q, net 'iobm/IOS_FSM_FFd3.Q' to DFF Setup(D) at 'IOACT.D' (GCK)
Target FF drives output net 'IOACT'
Setup to Clock at the Pad (tSU) : 7.5ns (0 macrocell levels)
Data signal 'CLK_IOB' to DFF D input Pin at 'IOACT.D'
Clock pad 'CLK2X_IOB' (GCK)
Minimum Clock Period: 11.0ns
Maximum Internal Clock Speed: 90.9Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A A A A A A A A A
\ _ _ _ _ _ _ _ _ _ _ _
\ F F F F F F F F F F F
\ S S S S S S S S S S S
\ B B B B B B B B B B B
\ < < < < < < < < < < <
\ 1 1 1 1 1 1 1 1 1 1 1
\ 0 1 2 3 4 5 6 7 8 9 >
\ > > > > > > > > > >
To \------------------------------------------------------------------
CLK20EN
CLK25EN
RA<0> 10.0 10.0
RA<10>
RA<11> 10.0
RA<1> 11.0
RA<2> 11.0
RA<3> 10.0
RA<4> 11.0
RA<5> 11.0
RA<6> 10.0
RA<7> 10.0
RA<8> 10.0
RA<9> 10.0
nBERR_FSB
nDinOE
nOE
nRAMLWE
nRAMUWE
nRAS
nROMCS
nROMWE
nVPA_FSB
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A A A A A A A A A
\ _ _ _ _ _ _ _ _ _ _ _
\ F F F F F F F F F F F
\ S S S S S S S S S S S
\ B B B B B B B B B B B
\ < < < < < < < < < < <
\ 2 2 2 2 2 3 4 5 6 7 8
\ 0 1 2 3 > > > > > > >
\ > > > >
To \------------------------------------------------------------------
CLK20EN
CLK25EN
RA<0>
RA<10> 10.0
RA<11>
RA<1> 11.0
RA<2> 11.0
RA<3> 10.0
RA<4> 11.0
RA<5> 11.0
RA<6> 10.0
RA<7> 10.0
RA<8> 11.0 11.0 11.0
RA<9> 10.0
nBERR_FSB 11.0 11.0 11.0 11.0
nDinOE 10.0 10.0 10.0 10.0
nOE
nRAMLWE
nRAMUWE
nRAS 11.0 11.0 11.0
nROMCS 11.0 11.0 11.0 11.0
nROMWE
nVPA_FSB
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A S S n n n n
\ _ W W A L U W
\ F < < S D D E
\ S 0 1 _ S S _
\ B > > F _ _ F
\ < S F F S
\ 9 B S S B
\ > B B
\
To \------------------------------------------
CLK20EN 10.0
CLK25EN 10.0
RA<0>
RA<10>
RA<11>
RA<1>
RA<2>
RA<3>
RA<4>
RA<5>
RA<6>
RA<7>
RA<8> 11.0
RA<9>
nBERR_FSB 10.0
nDinOE 10.0 10.0 10.0
nOE 10.0 10.0
nRAMLWE 10.0 10.0 10.0
nRAMUWE 11.0 11.0 11.0
nRAS 11.0
nROMCS 11.0
nROMWE 10.0 10.0
nVPA_FSB 10.0
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From C C
\ L L
\ K K
\ 2 _
\ X F
\ _ S
\ I B
\ O
\ B
\
To \------------
RA<0> 13.5
RA<1> 14.5
RA<2> 14.5
RA<3> 13.5
RA<4> 14.5
RA<5> 14.5
RA<6> 13.5
RA<7> 13.5
RA<8> 14.5
RA<9> 13.5
nADoutLE0 13.5 13.5
nADoutLE1 5.8
nAS_IOB 14.5
nAoutOE 5.8
nBERR_FSB 14.5
nBR_IOB 5.8
nCAS 5.8
nDTACK_FSB 5.8
nDinLE 5.8
nDoutOE 5.8
nLDS_IOB 14.5
nRAMLWE 13.5
nRAMUWE 14.5
nRAS 14.5
nROMCS 14.5
nUDS_IOB 14.5
nVMA_IOB 14.5
nVPA_FSB 13.5
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU or tSUF) (nsec)
\ From C C C
\ L L L
\ K K K
\ 2 _ _
\ X F I
\ _ S O
\ I B B
\ O
\ B
\
To \------------------
A_FSB<10> 7.9
A_FSB<11> 7.9
A_FSB<12> 7.9
A_FSB<13> 7.9
A_FSB<14> 7.9
A_FSB<15> 7.9
A_FSB<16> 7.9
A_FSB<17> 7.9
A_FSB<18> 7.9
A_FSB<19> 7.9
A_FSB<20> 15.6
A_FSB<21> 16.6
A_FSB<22> 16.6
A_FSB<23> 16.6
A_FSB<8> 7.9
A_FSB<9> 7.9
CLK_IOB 7.5
E_IOB 6.5
SW<1> 7.9
nAS_FSB 15.6
nBERR_IOB 7.5
nBG_IOB 6.5
nDTACK_IOB 6.5
nIPL2 6.5
nLDS_FSB 6.5
nRES 6.5 6.5
nUDS_FSB 6.5
nVPA_IOB 6.5
nWE_FSB 7.9
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK_FSB)
\ From B I I I R R R R R T
\ E O P P E E E E e i
\ R R L L S S S S f m
\ R W 2 2 D r r r A e
\ _ 0 r r o 0 1 2 c o
\ I . 0 1 n . . . k u
\ O Q . . e Q Q Q . t
\ B Q Q . Q A
\ S Q .
\ . Q
\ Q
\
\
\
\
\
\
\
To \------------------------------------------------------------
ALE0S.D
BERR_IOBS.D 10.0
IOL0.CE
IOL0.D
IOREQ.D
IORW0.D 11.4
IOU0.CE
IOU0.D
IPL2r1.D 10.0
RESDone.CE 10.0 10.0 10.0
RESr1.D 10.0
RESr2.D 10.0
RefAck.D
TimeoutA.D 10.0
TimeoutB.D
cnt/RefCnt<1>.D
cnt/RefCnt<2>.D
cnt/RefCnt<3>.D
cnt/RefCnt<4>.D
cnt/RefCnt<5>.D
cnt/RefCnt<6>.D
cnt/RefCnt<7>.D
cnt/RefDone.D 10.0
cnt/TimeoutBPre.D
cs/nOverlay0.D
cs/nOverlay1.CE
cs/nOverlay1.D
fsb/BERR0r.D
fsb/BERR1r.D 10.0
fsb/Ready0r.D
fsb/Ready1r.D
fsb/Ready2r.D 11.0
fsb/VPA.D 11.4 11.4
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOReady.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Once.D
iobs/PS_FSM_FFd1.D
iobs/PS_FSM_FFd2.D
nADoutLE1.D
nBR_IOB.CE 10.0 10.0 10.0 10.0 10.0 10.0
nCAS.D
nDTACK_FSB.D 11.4 11.4
ram/BACTr.D
ram/Once.D
ram/RAMDIS1.D
ram/RAMDIS2.D
ram/RAMReady.D
ram/RASEL.D
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK_FSB)
\ From T c c c c c c c c c
\ i n n n n n n n n n
\ m t t t t t t t t t
\ e / / / / / / / / /
\ o R R R R R R R R R
\ u e e e e e e e e e
\ t f f f f f f f f f
\ B C C C C C C C C D
\ . n n n n n n n n o
\ Q t t t t t t t t n
\ < < < < < < < < e
\ 0 1 2 3 4 5 6 7 .
\ > > > > > > > > Q
\ . . . . . . . .
\ Q Q Q Q Q Q Q Q
\
\
\
To \------------------------------------------------------------
ALE0S.D
BERR_IOBS.D
IOL0.CE
IOL0.D
IOREQ.D
IORW0.D
IOU0.CE
IOU0.D
IPL2r1.D
RESDone.CE
RESr1.D
RESr2.D
RefAck.D
TimeoutA.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
TimeoutB.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
cnt/RefCnt<1>.D 10.0
cnt/RefCnt<2>.D 10.0 10.0
cnt/RefCnt<3>.D 10.0 10.0 10.0
cnt/RefCnt<4>.D 10.0 10.0 10.0 10.0
cnt/RefCnt<5>.D 10.0 10.0 10.0 10.0 10.0
cnt/RefCnt<6>.D 10.0 10.0 10.0 10.0 10.0 10.0
cnt/RefCnt<7>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
cnt/RefDone.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
cnt/TimeoutBPre.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
cs/nOverlay0.D
cs/nOverlay1.CE
cs/nOverlay1.D
fsb/BERR0r.D 10.0
fsb/BERR1r.D
fsb/Ready0r.D
fsb/Ready1r.D
fsb/Ready2r.D
fsb/VPA.D 19.1
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOReady.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Once.D
iobs/PS_FSM_FFd1.D
iobs/PS_FSM_FFd2.D
nADoutLE1.D
nBR_IOB.CE
nCAS.D
nDTACK_FSB.D 19.1
ram/BACTr.D
ram/Once.D
ram/RAMDIS1.D 11.4 11.4 11.4 11.4
ram/RAMDIS2.D 11.0 11.0 11.0 11.0
ram/RAMReady.D 11.4 11.4 11.4 11.4
ram/RASEL.D 11.4 11.4 11.4 11.4
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D 11.4 11.4 11.4 11.4
ram/RS_FSM_FFd3.D 11.0 11.0 11.0 11.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK_FSB)
\ From c c c f f f f f f f
\ n s s s s s s s s s
\ t / / b b b b b b b
\ / n n / / / / / / /
\ T O O A B B R R R V
\ i v v S E E e e e P
\ m e e r R R a a a A
\ e r r f R R d d d .
\ o l l . 0 1 y y y Q
\ u a a Q r r 0 1 2
\ t y y . . r r r
\ B 0 1 Q Q . . .
\ P . . Q Q Q
\ r Q Q
\ e
\ .
\ Q
\
To \------------------------------------------------------------
ALE0S.D
BERR_IOBS.D 10.0
IOL0.CE
IOL0.D
IOREQ.D 11.0 10.0
IORW0.D 10.0 11.0
IOU0.CE
IOU0.D
IPL2r1.D
RESDone.CE
RESr1.D
RESr2.D
RefAck.D
TimeoutA.D 10.0
TimeoutB.D 10.0 10.0
cnt/RefCnt<1>.D
cnt/RefCnt<2>.D
cnt/RefCnt<3>.D
cnt/RefCnt<4>.D
cnt/RefCnt<5>.D
cnt/RefCnt<6>.D
cnt/RefCnt<7>.D
cnt/RefDone.D
cnt/TimeoutBPre.D 10.0 10.0
cs/nOverlay0.D 10.0 10.0
cs/nOverlay1.CE 10.0
cs/nOverlay1.D 10.0
fsb/BERR0r.D 10.0 10.0
fsb/BERR1r.D 10.0 10.0
fsb/Ready0r.D 10.0 10.0 10.0
fsb/Ready1r.D 11.0 10.0 11.0
fsb/Ready2r.D 11.0 11.0 11.0
fsb/VPA.D 20.1 19.1 11.4 11.4 20.1 11.4 11.4 11.4
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D 11.4 11.0
iobs/IOReady.D 10.0
iobs/IOU1.CE
iobs/Load1.D 11.0 10.0
iobs/Once.D 11.4 10.0
iobs/PS_FSM_FFd1.D
iobs/PS_FSM_FFd2.D 11.0 10.0
nADoutLE1.D
nBR_IOB.CE
nCAS.D
nDTACK_FSB.D 20.1 11.0 11.4 11.4 20.1 11.4 11.4
ram/BACTr.D 10.0
ram/Once.D 10.0 10.0
ram/RAMDIS1.D 11.4 11.0
ram/RAMDIS2.D 11.0 11.0
ram/RAMReady.D 11.0 11.0
ram/RASEL.D 11.4 11.4
ram/RS_FSM_FFd1.D 10.0 10.0
ram/RS_FSM_FFd2.D 11.4 11.4
ram/RS_FSM_FFd3.D 11.0 11.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK_FSB)
\ From i i i i i i i i i i
\ o o o o o o o o o o
\ b b b b b b b b b b
\ s s s s s s s s s s
\ / / / / / / / / / /
\ C I I I I I L O P P
\ l O O O O O o n S S
\ e A L R R U a c _ _
\ a C 1 W e 1 d e F F
\ r T . 1 a . 1 . S S
\ 1 r Q . d Q . Q M M
\ . . Q y Q _ _
\ Q Q . F F
\ Q F F
\ d d
\ 1 2
\ . .
\ Q Q
To \------------------------------------------------------------
ALE0S.D 10.0 10.0
BERR_IOBS.D 10.0 10.0 10.0
IOL0.CE 10.0 10.0
IOL0.D 10.0
IOREQ.D 10.0 10.0 10.0 11.0
IORW0.D 11.0 11.4 11.4 11.4
IOU0.CE 10.0 10.0
IOU0.D 10.0
IPL2r1.D
RESDone.CE
RESr1.D
RESr2.D
RefAck.D
TimeoutA.D
TimeoutB.D
cnt/RefCnt<1>.D
cnt/RefCnt<2>.D
cnt/RefCnt<3>.D
cnt/RefCnt<4>.D
cnt/RefCnt<5>.D
cnt/RefCnt<6>.D
cnt/RefCnt<7>.D
cnt/RefDone.D
cnt/TimeoutBPre.D
cs/nOverlay0.D
cs/nOverlay1.CE
cs/nOverlay1.D
fsb/BERR0r.D
fsb/BERR1r.D
fsb/Ready0r.D
fsb/Ready1r.D 11.0
fsb/Ready2r.D
fsb/VPA.D 11.4
iobs/Clear1.D 10.0 10.0
iobs/IOL1.CE 10.0
iobs/IORW1.D 10.0 10.0 11.0 11.0
iobs/IOReady.D 10.0 10.0 10.0 10.0
iobs/IOU1.CE 10.0
iobs/Load1.D 10.0 10.0 10.0
iobs/Once.D 11.4 11.0 10.0
iobs/PS_FSM_FFd1.D 10.0 10.0 10.0
iobs/PS_FSM_FFd2.D 10.0 10.0 11.0 11.0
nADoutLE1.D 10.0 10.0
nBR_IOB.CE
nCAS.D
nDTACK_FSB.D 11.4
ram/BACTr.D
ram/Once.D
ram/RAMDIS1.D
ram/RAMDIS2.D
ram/RAMReady.D
ram/RASEL.D
ram/RS_FSM_FFd1.D
ram/RS_FSM_FFd2.D
ram/RS_FSM_FFd3.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK_FSB)
\ From n n n r r r r r r r
\ A B D a a a a a a a
\ D R T m m m m m m m
\ o _ A / / / / / / /
\ u I C B O R R R R R
\ t O K A n A A A S S
\ L B _ C c M M S _ _
\ E . F T e D R E F F
\ 1 Q S r . I e L S S
\ . B . Q S a . M M
\ Q . Q 2 d Q _ _
\ Q . y F F
\ Q . F F
\ Q d d
\ 1 2
\ . .
\ Q Q
\
To \------------------------------------------------------------
ALE0S.D
BERR_IOBS.D 10.0
IOL0.CE
IOL0.D 10.0
IOREQ.D 11.0
IORW0.D 11.4
IOU0.CE
IOU0.D 10.0
IPL2r1.D
RESDone.CE
RESr1.D
RESr2.D
RefAck.D 10.0 10.0
TimeoutA.D
TimeoutB.D
cnt/RefCnt<1>.D
cnt/RefCnt<2>.D
cnt/RefCnt<3>.D
cnt/RefCnt<4>.D
cnt/RefCnt<5>.D
cnt/RefCnt<6>.D
cnt/RefCnt<7>.D
cnt/RefDone.D
cnt/TimeoutBPre.D
cs/nOverlay0.D
cs/nOverlay1.CE
cs/nOverlay1.D
fsb/BERR0r.D
fsb/BERR1r.D
fsb/Ready0r.D 10.0
fsb/Ready1r.D 11.0
fsb/Ready2r.D
fsb/VPA.D 11.0 11.4 20.1
iobs/Clear1.D 10.0
iobs/IOL1.CE
iobs/IORW1.D 10.0
iobs/IOReady.D 10.0
iobs/IOU1.CE
iobs/Load1.D 10.0
iobs/Once.D 11.0
iobs/PS_FSM_FFd1.D
iobs/PS_FSM_FFd2.D 11.0
nADoutLE1.D 10.0
nBR_IOB.CE
nCAS.D 10.0
nDTACK_FSB.D 11.0 11.4 11.4 20.1
ram/BACTr.D
ram/Once.D 10.0 10.0 10.0
ram/RAMDIS1.D 11.0 11.0 11.4 11.0
ram/RAMDIS2.D 11.0 11.0 11.0 11.0
ram/RAMReady.D 11.0 11.0 11.0 11.0
ram/RASEL.D 11.0 11.4 11.4 11.4
ram/RS_FSM_FFd1.D 10.0 10.0 10.0
ram/RS_FSM_FFd2.D 11.0 11.4 11.4
ram/RS_FSM_FFd3.D 10.0 11.0 11.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK_FSB)
\ From r
\ a
\ m
\ /
\ R
\ S
\ _
\ F
\ S
\ M
\ _
\ F
\ F
\ d
\ 3
\ .
\ Q
\
To \------
ALE0S.D
BERR_IOBS.D
IOL0.CE
IOL0.D
IOREQ.D
IORW0.D
IOU0.CE
IOU0.D
IPL2r1.D
RESDone.CE
RESr1.D
RESr2.D
RefAck.D
TimeoutA.D
TimeoutB.D
cnt/RefCnt<1>.D
cnt/RefCnt<2>.D
cnt/RefCnt<3>.D
cnt/RefCnt<4>.D
cnt/RefCnt<5>.D
cnt/RefCnt<6>.D
cnt/RefCnt<7>.D
cnt/RefDone.D
cnt/TimeoutBPre.D
cs/nOverlay0.D
cs/nOverlay1.CE
cs/nOverlay1.D
fsb/BERR0r.D
fsb/BERR1r.D
fsb/Ready0r.D
fsb/Ready1r.D
fsb/Ready2r.D
fsb/VPA.D
iobs/Clear1.D
iobs/IOL1.CE
iobs/IORW1.D
iobs/IOReady.D
iobs/IOU1.CE
iobs/Load1.D
iobs/Once.D
iobs/PS_FSM_FFd1.D
iobs/PS_FSM_FFd2.D
nADoutLE1.D
nBR_IOB.CE
nCAS.D
nDTACK_FSB.D
ram/BACTr.D
ram/Once.D 10.0
ram/RAMDIS1.D 11.0
ram/RAMDIS2.D 11.0
ram/RAMReady.D 11.0
ram/RASEL.D 11.0
ram/RS_FSM_FFd1.D 10.0
ram/RS_FSM_FFd2.D 11.4
ram/RS_FSM_FFd3.D 11.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK2X_IOB)
\ From I I i i i i i i i i
\ O O o o o o o o o o
\ A B b b b b b b b b
\ C E m m m m m m m m
\ T R / / / / / / / /
\ . R B B B B D D E E
\ Q . E E G G T T S S
\ Q R R r r A A < <
\ R R 0 1 C C 0 1
\ r r . . K K > >
\ f r Q Q r r . .
\ . . f r Q Q
\ Q Q . .
\ Q Q
\
\
\
\
\
To \------------------------------------------------------------
ALE0M.D
IOACT.D 10.0 10.0 11.0 11.0
IOBERR.D 11.0 11.0 11.0 11.0 11.0
iobm/BGr1.D 10.0
iobm/ES<0>.D 10.0 10.0
iobm/ES<1>.D 10.0 10.0
iobm/ES<2>.D 10.0 10.0
iobm/ES<3>.D 10.0 10.0
iobm/ES<4>.D 10.0 10.0
iobm/ETACK.D 10.0 10.0
iobm/IOS_FSM_FFd1.D
iobm/IOS_FSM_FFd2.D 10.0 10.0 10.0 10.0
iobm/IOS_FSM_FFd3.D
nAS_IOB.D
nAoutOE.D 10.0 10.0
nDinLE.D
nDoutOE.D
nLDS_IOB.D
nUDS_IOB.D
nVMA_IOB.D 10.0 10.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK2X_IOB)
\ From i i i i i i i i i i
\ o o o o o o o o o o
\ b b b b b b b b b b
\ m m m m m m m m m m
\ / / / / / / / / / /
\ E E E E E I I I I R
\ S S S T r O O O O E
\ < < < A 2 R S S S S
\ 2 3 4 C . E _ _ _ r
\ > > > K Q Q F F F f
\ . . . . r S S S .
\ Q Q Q Q . M M M Q
\ Q _ _ _
\ F F F
\ F F F
\ d d d
\ 1 2 3
\ . . .
\ Q Q Q
To \------------------------------------------------------------
ALE0M.D 10.0 10.0 10.0 10.0
IOACT.D 10.0 10.0 11.0 10.0 11.0 11.0
IOBERR.D 10.0 11.0 11.0 11.0 11.0
iobm/BGr1.D
iobm/ES<0>.D 10.0 10.0 10.0 10.0
iobm/ES<1>.D 10.0
iobm/ES<2>.D 10.0 10.0 10.0 10.0
iobm/ES<3>.D 10.0 10.0 10.0
iobm/ES<4>.D 10.0 10.0 10.0 10.0
iobm/ETACK.D 10.0 10.0 10.0
iobm/IOS_FSM_FFd1.D 10.0 10.0 10.0
iobm/IOS_FSM_FFd2.D 10.0 10.0 10.0 10.0 10.0
iobm/IOS_FSM_FFd3.D 10.0 10.0 10.0 10.0
nAS_IOB.D 10.0 10.0 10.0
nAoutOE.D
nDinLE.D 10.0 10.0
nDoutOE.D 10.0 10.0
nLDS_IOB.D 10.0 10.0 10.0
nUDS_IOB.D 10.0 10.0 10.0
nVMA_IOB.D 10.0 10.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK2X_IOB)
\ From i i i n n n
\ o o o A A V
\ b b b S o M
\ m m m _ u A
\ / / / I t _
\ R V V O O I
\ E P P B E O
\ S A A . . B
\ r r r Q Q .
\ r f r Q
\ . . .
\ Q Q Q
\
\
\
\
\
\
\
To \------------------------------------
ALE0M.D 10.0
IOACT.D 11.0 10.0
IOBERR.D 11.0
iobm/BGr1.D
iobm/ES<0>.D
iobm/ES<1>.D
iobm/ES<2>.D
iobm/ES<3>.D
iobm/ES<4>.D
iobm/ETACK.D 10.0
iobm/IOS_FSM_FFd1.D
iobm/IOS_FSM_FFd2.D 10.0
iobm/IOS_FSM_FFd3.D 10.0
nAS_IOB.D
nAoutOE.D 10.0 10.0
nDinLE.D
nDoutOE.D
nLDS_IOB.D
nUDS_IOB.D
nVMA_IOB.D 10.0 10.0 10.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and ends at register
(Fast Input Register for tSUF) D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers. Pin-to-pin setup
requirement is not reported or
guaranteed for product-term clocks
derived from macrocell feedback
signals.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU. Note that
when the computed Maximum Clock Speed
is limited by tCYC it is computed
assuming that all registers are
rising-edge sensitive.