Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'WarpSE.ise'. Inferring BUFG constraint for signal 'C16M' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. Inferring BUFG constraint for signal 'C8M' based upon the LOC constraint 'P23'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. Inferring BUFG constraint for signal 'FCLK' based upon the LOC constraint 'P27'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. Removing unused input(s) 'C20MEN'. The input(s) are unused after optimization. Please verify functionality via simulation. Removing unused input(s) 'SW<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. Removing unused input(s) 'SW<2>'. The input(s) are unused after optimization. Please verify functionality via simulation. Removing unused input(s) 'SW<3>'. The input(s) are unused after optimization. Please verify functionality via simulation. Removing unused input(s) 'nBG_IOB'. The input(s) are unused after optimization. Please verify functionality via simulation.