Design Name | MXSE |
Fitting Status | Successful |
Software Version | P.20131013 |
Device Used | XC95144XL-10-TQ100 |
Date | 12-11-2021, 6:24AM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
110/144 (77%) | 439/720 (61%) | 84/144 (59%) | 67/81 (83%) | 244/432 (57%) |
|
|
Signal mapped onto global clock net (GCK1) | CLK2X_IOB |
Signal mapped onto global clock net (GCK2) | CLK_FSB |
Signal mapped onto global clock net (GCK3) | CLK_IOB |
Signal mapped onto global output enable net (GSR) | nRES |
Macrocells in high performance mode (MCHP) | 110 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 110 |