Register <QoSEN> in unit <CNT> has a constant value of 1 during circuit operation. The register is replaced by logic. Input <A<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <IOS0> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <nRESr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <VIACSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <SndCSWRr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <SCSICSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <SCCCSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <IWMCSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <IACK1CSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <IACK0CSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <DBG> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <nPOR> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Due to constant pushing, FF/Latch <0> is unconnected in block <RAMReadyReg>. Node <RAMReadyReg> of sequential type is unconnected in block <ram>.