cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: WarpSE Date: 4- 7-2023, 0:29AM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 115/144 ( 80%) 286 /720 ( 40%) 209/432 ( 48%) 92 /144 ( 64%) 63 /81 ( 78%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 9/18 28/54 37/90 11/11* FB2 4/18 9/54 8/90 4/10 FB3 15/18 29/54 35/90 10/10* FB4 18/18* 29/54 63/90 6/10 FB5 18/18* 29/54 29/90 8/10 FB6 15/18 28/54 38/90 10/10* FB7 18/18* 28/54 34/90 8/10 FB8 18/18* 29/54 42/90 6/10 ----- ----- ----- ----- 115/144 209/432 286/720 63/81 * - Resource is exhausted ** Global Control Resources ** Signal 'C16M' mapped onto global clock net GCK1. Signal 'C8M' mapped onto global clock net GCK2. Signal 'FCLK' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 24 24 | I/O : 60 73 Output : 35 35 | GCK/IO : 3 3 Bidirectional : 1 1 | GTS/IO : 0 4 GCK : 3 3 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 63 63 ** Power Data ** There are 115 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'WarpSE.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC constraint 'P23'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC constraint 'P27'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<2>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<3>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<4>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<5>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<6>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<7>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'A_FSB<8>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'SW<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'SW<2>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'SW<3>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 36 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State nDTACK_FSB 7 11 FB3_9 28 I/O O STD FAST RESET nROMWE 1 2 FB3_17 34 I/O O STD FAST nAoutOE 2 4 FB4_2 87 I/O O STD FAST SET nDoutOE 2 5 FB4_5 89 I/O O STD FAST nDinOE 4 7 FB4_6 90 I/O O STD FAST nRES 1 1 FB4_8 91 I/O I/O STD FAST nVPA_FSB 3 9 FB4_11 93 I/O O STD FAST RESET nROMCS 2 5 FB5_2 35 I/O O STD FAST nCAS 1 1 FB5_5 36 I/O O STD FAST RESET nOE 1 2 FB5_6 37 I/O O STD FAST RA<4> 1 1 FB5_9 40 I/O O STD FAST RA<3> 1 1 FB5_11 41 I/O O STD FAST RA<5> 1 1 FB5_12 42 I/O O STD FAST RA<2> 1 1 FB5_14 43 I/O O STD FAST RA<6> 1 1 FB5_15 46 I/O O STD FAST nVMA_IOB 3 8 FB6_2 74 I/O O STD FAST RESET nLDS_IOB 6 10 FB6_9 79 I/O O STD FAST RESET nUDS_IOB 6 10 FB6_11 80 I/O O STD FAST RESET nAS_IOB 4 9 FB6_12 81 I/O O STD FAST RESET nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET nADoutLE0 1 2 FB6_15 85 I/O O STD FAST nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET RA<1> 1 1 FB7_2 50 I/O O STD FAST RA<7> 1 1 FB7_5 52 I/O O STD FAST RA<0> 1 1 FB7_6 53 I/O O STD FAST RA<8> 1 1 FB7_8 54 I/O O STD FAST RA<10> 1 1 FB7_9 55 I/O O STD FAST RA<9> 1 1 FB7_11 56 I/O O STD FAST C25MEN 0 0 FB7_12 58 I/O O STD FAST C20MEN 0 0 FB7_14 59 I/O O STD FAST RA<11> 1 1 FB8_2 63 I/O O STD FAST nRAS 1 2 FB8_5 64 I/O O STD FAST SET nRAMLWE 1 4 FB8_6 65 I/O O STD FAST nRAMUWE 1 4 FB8_8 66 I/O O STD FAST nBERR_FSB 3 5 FB8_12 70 I/O O STD FAST RESET nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET ** 79 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State iobm/Er 1 1 FB1_1 STD RESET cs/nOverlay 2 5 FB1_11 STD RESET iobm/ES<2> 3 5 FB1_12 STD RESET iobm/ES<0> 3 6 FB1_13 STD RESET iobm/ES<3> 4 6 FB1_14 STD RESET iobm/ES<1> 4 6 FB1_15 STD RESET IODONE 4 8 FB1_16 STD RESET IOU0 8 14 FB1_17 STD RESET IOL0 8 14 FB1_18 STD RESET iobm/VPAr 1 1 FB2_15 STD RESET cnt/nIPL2r 1 1 FB2_16 STD RESET IOBERR 2 2 FB2_17 STD RESET cnt/Timer<1> 4 5 FB2_18 STD RESET ram/RS_FSM_FFd4 1 1 FB3_4 STD RESET ram/RS_FSM_FFd1 1 1 FB3_5 STD RESET iobs/IODONEr<0> 1 1 FB3_6 STD RESET cnt/INITS_FSM_FFd1 1 7 FB3_7 STD RESET cnt/Er<0> 1 1 FB3_8 STD RESET cnt/TimerTC 2 6 FB3_10 STD RESET cnt/LTimer<3> 2 6 FB3_11 STD RESET cnt/LTimer<2> 2 5 FB3_12 STD RESET cnt/LTimer<1> 2 4 FB3_13 STD RESET cnt/INITS_FSM_FFd2 2 6 FB3_14 STD RESET RefReq 2 5 FB3_15 STD RESET cnt/Timer<2> 5 6 FB3_16 STD RESET RefUrg 5 7 FB3_18 STD RESET ram/BACTr 1 2 FB4_1 STD RESET nRESout 1 2 FB4_3 STD RESET iobs/Clear1 1 2 FB4_4 STD RESET ram/Once 2 2 FB4_7 STD RESET iobs/TS_FSM_FFd1 2 3 FB4_9 STD RESET cs/ODCSr 2 6 FB4_10 STD RESET IOWRREQ 8 15 FB4_12 STD RESET iobs/Load1 4 9 FB4_13 STD RESET iobs/IORW1 4 10 FB4_14 STD RESET IONPReady 4 8 FB4_15 STD RESET iobs/TS_FSM_FFd2 5 12 FB4_16 STD RESET IORDREQ 8 15 FB4_17 STD RESET iobs/Sent 9 12 FB4_18 STD RESET cnt/LTimerTC 2 16 FB5_1 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State cnt/LTimer<9> 2 12 FB5_3 STD RESET cnt/LTimer<8> 2 11 FB5_4 STD RESET cnt/LTimer<7> 2 10 FB5_7 STD RESET cnt/LTimer<6> 2 9 FB5_8 STD RESET cnt/LTimer<5> 2 8 FB5_10 STD RESET cnt/LTimer<4> 2 7 FB5_13 STD RESET cnt/LTimer<12> 2 15 FB5_16 STD RESET cnt/LTimer<11> 2 14 FB5_17 STD RESET cnt/LTimer<10> 2 13 FB5_18 STD RESET iobs/IOACTr 1 1 FB6_5 STD RESET iobm/IOS_FSM_FFd5 1 1 FB6_6 STD RESET iobm/IOS_FSM_FFd4 1 1 FB6_7 STD RESET iobm/IOS_FSM_FFd1 1 1 FB6_8 STD RESET iobm/C8Mr 1 1 FB6_10 STD RESET iobm/IOS_FSM_FFd6 2 5 FB6_13 STD RESET iobm/IOS_FSM_FFd7 3 6 FB6_16 STD SET ALE0M 5 11 FB6_18 STD RESET iobm/IOWRREQr 1 1 FB7_1 STD RESET iobm/IORDREQr 1 1 FB7_3 STD RESET cnt/LTimer<0> 1 3 FB7_4 STD RESET cnt/Er<1> 1 1 FB7_7 STD RESET iobm/IOS_FSM_FFd2 2 4 FB7_10 STD RESET cnt/Timer<0> 2 4 FB7_13 STD RESET iobm/IOS_FSM_FFd3 3 5 FB7_15 STD RESET iobm/DoutOE 4 8 FB7_16 STD RESET iobm/IOS0 5 12 FB7_17 STD RESET IOACT 8 14 FB7_18 STD RESET ram/RS_FSM_FFd3 1 1 FB8_1 STD RESET ram/RS_FSM_FFd2 1 1 FB8_3 STD RESET fsb/ASrf 1 1 FB8_4 STD RESET ALE0S 1 1 FB8_7 STD RESET ram/RefDone 2 5 FB8_9 STD RESET iobs/IOU1 2 2 FB8_10 STD RESET iobs/IOL1 2 2 FB8_11 STD RESET IOPWReady 2 5 FB8_13 STD RESET ram/RS_FSM_FFd6 4 8 FB8_14 STD RESET ram/RS_FSM_FFd8 5 9 FB8_16 STD SET ram/CAS 5 9 FB8_17 STD RESET ram/RAMEN 7 10 FB8_18 STD RESET ** 27 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use A_FSB<13> FB1_2 11 I/O I A_FSB<14> FB1_3 12 I/O I A_FSB<15> FB1_5 13 I/O I A_FSB<16> FB1_6 14 I/O I A_FSB<17> FB1_8 15 I/O I A_FSB<18> FB1_9 16 I/O I A_FSB<19> FB1_11 17 I/O I A_FSB<20> FB1_12 18 I/O I A_FSB<21> FB1_14 19 I/O I A_FSB<22> FB1_15 20 I/O I C16M FB1_17 22 GCK/I/O GCK A_FSB<9> FB2_12 7 I/O I A_FSB<10> FB2_14 8 I/O I A_FSB<11> FB2_15 9 I/O I A_FSB<12> FB2_17 10 I/O I C8M FB3_2 23 GCK/I/O GCK/I A_FSB<23> FB3_5 24 I/O I E FB3_6 25 I/O I FCLK FB3_8 27 GCK/I/O GCK nWE_FSB FB3_11 29 I/O I nLDS_FSB FB3_12 30 I/O I nAS_FSB FB3_14 32 I/O I nUDS_FSB FB3_15 33 I/O I nIPL2 FB4_9 92 I/O I nBERR_IOB FB6_5 76 I/O I nVPA_IOB FB6_6 77 I/O I nDTACK_IOB FB6_8 78 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use iobm/Er 1 0 /\4 0 FB1_1 (b) (b) (unused) 0 0 0 5 FB1_2 11 I/O I (unused) 0 0 0 5 FB1_3 12 I/O I (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 13 I/O I (unused) 0 0 0 5 FB1_6 14 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 15 I/O I (unused) 0 0 0 5 FB1_9 16 I/O I (unused) 0 0 0 5 FB1_10 (b) cs/nOverlay 2 0 0 3 FB1_11 17 I/O I iobm/ES<2> 3 0 0 2 FB1_12 18 I/O I iobm/ES<0> 3 0 0 2 FB1_13 (b) (b) iobm/ES<3> 4 0 0 1 FB1_14 19 I/O I iobm/ES<1> 4 0 \/1 0 FB1_15 20 I/O I IODONE 4 1<- \/2 0 FB1_16 (b) (b) IOU0 8 3<- 0 0 FB1_17 22 GCK/I/O GCK IOL0 8 4<- /\1 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: A_FSB<20> 11: fsb/ASrf 20: iobs/TS_FSM_FFd1 2: A_FSB<21> 12: iobm/ES<0> 21: iobs/TS_FSM_FFd2 3: A_FSB<22> 13: iobm/ES<1> 22: nADoutLE1 4: A_FSB<23> 14: iobm/ES<2> 23: nAS_FSB 5: E 15: iobm/ES<3> 24: nAS_IOB 6: IOL0 16: iobm/Er 25: nDTACK_IOB 7: IOU0 17: iobs/IOL1 26: nLDS_FSB 8: nRES.PIN 18: iobs/IOU1 27: nUDS_FSB 9: cs/ODCSr 19: iobs/Sent 28: nVMA_IOB 10: cs/nOverlay Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs iobm/Er ....X................................... 1 cs/nOverlay .......XXXX...........X................. 5 iobm/ES<2> ....X......XXX.X........................ 5 iobm/ES<0> ....X......XXXXX........................ 6 iobm/ES<3> ....X......XXXXX........................ 6 iobm/ES<1> ....X......XXXXX........................ 6 IODONE .......X...XXXX........XX..X............ 8 IOU0 XXXX..X..XX......XXXXXX...X............. 14 IOL0 XXXX.X...XX.....X.XXXXX..X.............. 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 9/45 Number of signals used by logic mapping into function block: 9 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 99 GSR/I/O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 1 GTS/I/O (unused) 0 0 0 5 FB2_6 2 GTS/I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 3 GTS/I/O (unused) 0 0 0 5 FB2_9 4 GTS/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 6 I/O (unused) 0 0 0 5 FB2_12 7 I/O I (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 8 I/O I iobm/VPAr 1 0 0 4 FB2_15 9 I/O I cnt/nIPL2r 1 0 0 4 FB2_16 (b) (b) IOBERR 2 0 0 3 FB2_17 10 I/O I cnt/Timer<1> 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: cnt/Er<0> 4: cnt/Timer<1> 7: nBERR_IOB 2: cnt/Er<1> 5: cnt/TimerTC 8: nIPL2 3: cnt/Timer<0> 6: nAS_IOB 9: nVPA_IOB Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs iobm/VPAr ........X............................... 1 cnt/nIPL2r .......X................................ 1 IOBERR .....XX................................. 2 cnt/Timer<1> XXXXX................................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 23 GCK/I/O GCK/I (unused) 0 0 0 5 FB3_3 (b) ram/RS_FSM_FFd4 1 0 0 4 FB3_4 (b) (b) ram/RS_FSM_FFd1 1 0 0 4 FB3_5 24 I/O I iobs/IODONEr<0> 1 0 0 4 FB3_6 25 I/O I cnt/INITS_FSM_FFd1 1 0 0 4 FB3_7 (b) (b) cnt/Er<0> 1 0 \/1 3 FB3_8 27 GCK/I/O GCK nDTACK_FSB 7 2<- 0 0 FB3_9 28 I/O O cnt/TimerTC 2 0 /\1 2 FB3_10 (b) (b) cnt/LTimer<3> 2 0 0 3 FB3_11 29 I/O I cnt/LTimer<2> 2 0 0 3 FB3_12 30 I/O I cnt/LTimer<1> 2 0 0 3 FB3_13 (b) (b) cnt/INITS_FSM_FFd2 2 0 0 3 FB3_14 32 I/O I RefReq 2 0 0 3 FB3_15 33 I/O I cnt/Timer<2> 5 0 0 0 FB3_16 (b) (b) nROMWE 1 0 0 4 FB3_17 34 I/O O RefUrg 5 0 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: A_FSB<18> 11: RefUrg 21: cnt/Timer<1> 2: A_FSB<19> 12: cnt/Er<0> 22: cnt/Timer<2> 3: A_FSB<20> 13: cnt/Er<1> 23: cnt/TimerTC 4: A_FSB<21> 14: cnt/INITS_FSM_FFd1 24: cnt/nIPL2r 5: A_FSB<22> 15: cnt/INITS_FSM_FFd2 25: fsb/ASrf 6: A_FSB<23> 16: cnt/LTimer<0> 26: nAS_FSB 7: E 17: cnt/LTimer<1> 27: nWE_FSB 8: IODONE 18: cnt/LTimer<2> 28: ram/RS_FSM_FFd1 9: IONPReady 19: cnt/LTimerTC 29: ram/RS_FSM_FFd2 10: IOPWReady 20: cnt/Timer<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ram/RS_FSM_FFd4 ...........................X............ 1 ram/RS_FSM_FFd1 ............................X........... 1 iobs/IODONEr<0> .......X................................ 1 cnt/INITS_FSM_FFd1 ...........XXXX...X...XX................ 7 cnt/Er<0> ......X................................. 1 nDTACK_FSB XXXXXX..XX..............XXX............. 11 cnt/TimerTC ..........XXX......XXX.................. 6 cnt/LTimer<3> ...........XX..XXX....X................. 6 cnt/LTimer<2> ...........XX..XX.....X................. 5 cnt/LTimer<1> ...........XX..X......X................. 4 cnt/INITS_FSM_FFd2 ...........XXXX...X...X................. 6 RefReq ..........XXX.......XX.................. 5 cnt/Timer<2> ...........XX......XXXX................. 6 nROMWE .........................XX............. 2 RefUrg ..........XXX......XXXX................. 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ram/BACTr 1 1<- /\5 0 FB4_1 (b) (b) nAoutOE 2 0 /\1 2 FB4_2 87 I/O O nRESout 1 0 0 4 FB4_3 (b) (b) iobs/Clear1 1 0 0 4 FB4_4 (b) (b) nDoutOE 2 0 0 3 FB4_5 89 I/O O nDinOE 4 0 0 1 FB4_6 90 I/O O ram/Once 2 0 0 3 FB4_7 (b) (b) nRES 1 0 0 4 FB4_8 91 I/O I/O iobs/TS_FSM_FFd1 2 0 0 3 FB4_9 92 I/O I cs/ODCSr 2 0 0 3 FB4_10 (b) (b) nVPA_FSB 3 0 \/2 0 FB4_11 93 I/O O IOWRREQ 8 3<- 0 0 FB4_12 94 I/O (b) iobs/Load1 4 0 /\1 0 FB4_13 (b) (b) iobs/IORW1 4 0 \/1 0 FB4_14 95 I/O (b) IONPReady 4 1<- \/2 0 FB4_15 96 I/O (b) iobs/TS_FSM_FFd2 5 2<- \/2 0 FB4_16 (b) (b) IORDREQ 8 3<- 0 0 FB4_17 97 I/O (b) iobs/Sent 9 5<- /\1 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: A_FSB<18> 11: cnt/INITS_FSM_FFd2 21: iobs/Sent 2: A_FSB<19> 12: cs/nOverlay 22: iobs/TS_FSM_FFd1 3: A_FSB<20> 13: fsb/ASrf 23: iobs/TS_FSM_FFd2 4: A_FSB<21> 14: iobm/DoutOE 24: nADoutLE1 5: A_FSB<22> 15: iobm/IORDREQr 25: nAS_FSB 6: A_FSB<23> 16: iobm/IOS0 26: nAoutOE 7: IONPReady 17: iobm/IOWRREQr 27: nBR_IOB 8: IORDREQ 18: iobs/IOACTr 28: nRESout 9: IOWRREQ 19: iobs/IODONEr<0> 29: nWE_FSB 10: cnt/INITS_FSM_FFd1 20: iobs/IORW1 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ram/BACTr ............X...........X............... 2 nAoutOE .........XX..............XX............. 4 nRESout .........XX............................. 2 iobs/Clear1 .....................XX................. 2 nDoutOE .............XXXX........X.............. 5 nDinOE ..XXXX.....X............X...X........... 7 ram/Once ............X...........X............... 2 nRES ...........................X............ 1 iobs/TS_FSM_FFd1 .................X...XX................. 3 cs/ODCSr ..XXXX......X...........X............... 6 nVPA_FSB XXXXXXX.....X...........X............... 9 IOWRREQ ..XXXX..X..XX....X.XXXXXX...X........... 15 iobs/Load1 ....XX......X.......XXXXX...X........... 9 iobs/IORW1 ....XX......X......XXXXXX...X........... 10 IONPReady ....XXX.....X.....X.X...X...X........... 8 iobs/TS_FSM_FFd2 ..XXXX.....XX....X..XXXXX............... 12 IORDREQ ..XXXX.X...XX....X.XXXXXX...X........... 15 iobs/Sent ..XXXX.....XX.......XXXXX...X........... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use cnt/LTimerTC 2 0 0 3 FB5_1 (b) (b) nROMCS 2 0 0 3 FB5_2 35 I/O O cnt/LTimer<9> 2 0 0 3 FB5_3 (b) (b) cnt/LTimer<8> 2 0 0 3 FB5_4 (b) (b) nCAS 1 0 0 4 FB5_5 36 I/O O nOE 1 0 0 4 FB5_6 37 I/O O cnt/LTimer<7> 2 0 0 3 FB5_7 (b) (b) cnt/LTimer<6> 2 0 0 3 FB5_8 39 I/O (b) RA<4> 1 0 0 4 FB5_9 40 I/O O cnt/LTimer<5> 2 0 0 3 FB5_10 (b) (b) RA<3> 1 0 0 4 FB5_11 41 I/O O RA<5> 1 0 0 4 FB5_12 42 I/O O cnt/LTimer<4> 2 0 0 3 FB5_13 (b) (b) RA<2> 1 0 0 4 FB5_14 43 I/O O RA<6> 1 0 0 4 FB5_15 46 I/O O cnt/LTimer<12> 2 0 0 3 FB5_16 (b) (b) cnt/LTimer<11> 2 0 0 3 FB5_17 49 I/O (b) cnt/LTimer<10> 2 0 0 3 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: A_FSB<11> 11: cnt/Er<1> 21: cnt/LTimer<6> 2: A_FSB<12> 12: cnt/LTimer<0> 22: cnt/LTimer<7> 3: A_FSB<13> 13: cnt/LTimer<10> 23: cnt/LTimer<8> 4: A_FSB<16> 14: cnt/LTimer<11> 24: cnt/LTimer<9> 5: A_FSB<19> 15: cnt/LTimer<12> 25: cnt/TimerTC 6: A_FSB<20> 16: cnt/LTimer<1> 26: cs/nOverlay 7: A_FSB<21> 17: cnt/LTimer<2> 27: nAS_FSB 8: A_FSB<22> 18: cnt/LTimer<3> 28: nWE_FSB 9: A_FSB<23> 19: cnt/LTimer<4> 29: ram/CAS 10: cnt/Er<0> 20: cnt/LTimer<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs cnt/LTimerTC .........XXXXXXXXXXXXXXXX............... 16 nROMCS .....XXXX................X.............. 5 cnt/LTimer<9> .........XXX...XXXXXXXX.X............... 12 cnt/LTimer<8> .........XXX...XXXXXXX..X............... 11 nCAS ............................X........... 1 nOE ..........................XX............ 2 cnt/LTimer<7> .........XXX...XXXXXX...X............... 10 cnt/LTimer<6> .........XXX...XXXXX....X............... 9 RA<4> X....................................... 1 cnt/LTimer<5> .........XXX...XXXX.....X............... 8 RA<3> ....X................................... 1 RA<5> .X...................................... 1 cnt/LTimer<4> .........XXX...XXX......X............... 7 RA<2> ...X.................................... 1 RA<6> ..X..................................... 1 cnt/LTimer<12> .........XXXXX.XXXXXXXXXX............... 15 cnt/LTimer<11> .........XXXX..XXXXXXXXXX............... 14 cnt/LTimer<10> .........XXX...XXXXXXXXXX............... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) nVMA_IOB 3 0 0 2 FB6_2 74 I/O O (unused) 0 0 0 5 FB6_3 (b) (unused) 0 0 0 5 FB6_4 (b) iobs/IOACTr 1 0 0 4 FB6_5 76 I/O I iobm/IOS_FSM_FFd5 1 0 0 4 FB6_6 77 I/O I iobm/IOS_FSM_FFd4 1 0 0 4 FB6_7 (b) (b) iobm/IOS_FSM_FFd1 1 0 \/1 3 FB6_8 78 I/O I nLDS_IOB 6 1<- 0 0 FB6_9 79 I/O O iobm/C8Mr 1 0 \/1 3 FB6_10 (b) (b) nUDS_IOB 6 1<- 0 0 FB6_11 80 I/O O nAS_IOB 4 0 0 1 FB6_12 81 I/O O iobm/IOS_FSM_FFd6 2 0 0 3 FB6_13 (b) (b) nADoutLE1 2 0 0 3 FB6_14 82 I/O O nADoutLE0 1 0 0 4 FB6_15 85 I/O O iobm/IOS_FSM_FFd7 3 0 0 2 FB6_16 (b) (b) nDinLE 1 0 0 4 FB6_17 86 I/O O ALE0M 5 0 0 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: ALE0M 11: iobm/ES<3> 20: iobm/IOWRREQr 2: ALE0S 12: iobm/IORDREQr 21: iobm/VPAr 3: C8M 13: iobm/IOS_FSM_FFd1 22: iobs/Clear1 4: IOACT 14: iobm/IOS_FSM_FFd2 23: iobs/Load1 5: IOL0 15: iobm/IOS_FSM_FFd3 24: nADoutLE1 6: IOU0 16: iobm/IOS_FSM_FFd4 25: nAoutOE 7: iobm/C8Mr 17: iobm/IOS_FSM_FFd5 26: nLDS_IOB 8: iobm/ES<0> 18: iobm/IOS_FSM_FFd6 27: nUDS_IOB 9: iobm/ES<1> 19: iobm/IOS_FSM_FFd7 28: nVMA_IOB 10: iobm/ES<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs nVMA_IOB ...X...XXXX.........X...X..X............ 8 iobs/IOACTr ...X.................................... 1 iobm/IOS_FSM_FFd5 .................X...................... 1 iobm/IOS_FSM_FFd4 ................X....................... 1 iobm/IOS_FSM_FFd1 .............X.......................... 1 nLDS_IOB ....X.X....X..XXXXX.....XX.............. 10 iobm/C8Mr ..X..................................... 1 nUDS_IOB .....XX....X..XXXXX.....X.X............. 10 nAS_IOB ......X....X..XXXXXX....X............... 9 iobm/IOS_FSM_FFd6 ......X....X......XX....X............... 5 nADoutLE1 .....................XXX................ 3 nADoutLE0 XX...................................... 2 iobm/IOS_FSM_FFd7 ......X....XX.....XX....X............... 6 nDinLE ..............XX........................ 2 ALE0M X..........XXXXXXXXX....X............... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use iobm/IOWRREQr 1 0 /\3 1 FB7_1 (b) (b) RA<1> 1 0 0 4 FB7_2 50 I/O O iobm/IORDREQr 1 0 0 4 FB7_3 (b) (b) cnt/LTimer<0> 1 0 0 4 FB7_4 (b) (b) RA<7> 1 0 0 4 FB7_5 52 I/O O RA<0> 1 0 0 4 FB7_6 53 I/O O cnt/Er<1> 1 0 0 4 FB7_7 (b) (b) RA<8> 1 0 0 4 FB7_8 54 I/O O RA<10> 1 0 0 4 FB7_9 55 I/O O iobm/IOS_FSM_FFd2 2 0 0 3 FB7_10 (b) (b) RA<9> 1 0 0 4 FB7_11 56 I/O O C25MEN 0 0 0 5 FB7_12 58 I/O O cnt/Timer<0> 2 0 0 3 FB7_13 (b) (b) C20MEN 0 0 0 5 FB7_14 59 I/O O iobm/IOS_FSM_FFd3 3 0 0 2 FB7_15 60 I/O (b) iobm/DoutOE 4 0 0 1 FB7_16 (b) (b) iobm/IOS0 5 0 0 0 FB7_17 61 I/O (b) IOACT 8 3<- 0 0 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: A_FSB<10> 11: IOWRREQ 20: iobm/IOS_FSM_FFd1 2: A_FSB<14> 12: cnt/Er<0> 21: iobm/IOS_FSM_FFd2 3: A_FSB<15> 13: cnt/Er<1> 22: iobm/IOS_FSM_FFd3 4: A_FSB<17> 14: cnt/Timer<0> 23: iobm/IOS_FSM_FFd4 5: A_FSB<18> 15: cnt/TimerTC 24: iobm/IOS_FSM_FFd5 6: A_FSB<9> 16: iobm/C8Mr 25: iobm/IOS_FSM_FFd6 7: IOACT 17: iobm/DoutOE 26: iobm/IOS_FSM_FFd7 8: IOBERR 18: iobm/IORDREQr 27: iobm/IOWRREQr 9: IODONE 19: iobm/IOS0 28: nAoutOE 10: IORDREQ Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs iobm/IOWRREQr ..........X............................. 1 RA<1> X....................................... 1 iobm/IORDREQr .........X.............................. 1 cnt/LTimer<0> ...........XX.X......................... 3 RA<7> .X...................................... 1 RA<0> .....X.................................. 1 cnt/Er<1> ...........X............................ 1 RA<8> ....X................................... 1 RA<10> ...X.................................... 1 iobm/IOS_FSM_FFd2 .......XX......X.....X.................. 4 RA<9> ..X..................................... 1 C25MEN ........................................ 0 cnt/Timer<0> ...........XXXX......................... 4 C20MEN ........................................ 0 iobm/IOS_FSM_FFd3 .......XX......X.....XX................. 5 iobm/DoutOE ...............XX....XXXXXX............. 8 iobm/IOS0 ...............X.XXXXXXXXXXX............ 12 IOACT ......XXX......X.X.XXXXXXXXX............ 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ram/RS_FSM_FFd3 1 0 /\2 2 FB8_1 (b) (b) RA<11> 1 0 0 4 FB8_2 63 I/O O ram/RS_FSM_FFd2 1 0 0 4 FB8_3 (b) (b) fsb/ASrf 1 0 0 4 FB8_4 (b) (b) nRAS 1 0 0 4 FB8_5 64 I/O O nRAMLWE 1 0 0 4 FB8_6 65 I/O O ALE0S 1 0 0 4 FB8_7 (b) (b) nRAMUWE 1 0 0 4 FB8_8 66 I/O O ram/RefDone 2 0 0 3 FB8_9 67 I/O (b) iobs/IOU1 2 0 0 3 FB8_10 (b) (b) iobs/IOL1 2 0 0 3 FB8_11 68 I/O (b) nBERR_FSB 3 0 0 2 FB8_12 70 I/O O IOPWReady 2 0 0 3 FB8_13 (b) (b) ram/RS_FSM_FFd6 4 0 0 1 FB8_14 71 I/O (b) nBR_IOB 2 0 0 3 FB8_15 72 I/O O ram/RS_FSM_FFd8 5 0 0 0 FB8_16 (b) (b) ram/CAS 5 0 0 0 FB8_17 73 I/O (b) ram/RAMEN 7 2<- 0 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: A_FSB<19> 11: iobs/Load1 21: ram/BACTr 2: IOBERR 12: iobs/Sent 22: ram/Once 3: IOPWReady 13: iobs/TS_FSM_FFd2 23: ram/RAMEN 4: RefReq 14: nADoutLE1 24: ram/RS_FSM_FFd2 5: RefUrg 15: nAS_FSB 25: ram/RS_FSM_FFd3 6: cnt/INITS_FSM_FFd1 16: nBERR_FSB 26: ram/RS_FSM_FFd4 7: cnt/INITS_FSM_FFd2 17: nBR_IOB 27: ram/RS_FSM_FFd6 8: cnt/nIPL2r 18: nLDS_FSB 28: ram/RS_FSM_FFd8 9: fsb/ASrf 19: nUDS_FSB 29: ram/RefDone 10: iobs/Clear1 20: nWE_FSB Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ram/RS_FSM_FFd3 ..........................X............. 1 RA<11> X....................................... 1 ram/RS_FSM_FFd2 ........................X............... 1 fsb/ASrf ..............X......................... 1 nRAS ........................X.X............. 2 nRAMLWE ..............X..X.X..X................. 4 ALE0S ............X........................... 1 nRAMUWE ..............X...XX..X................. 4 ram/RefDone ...XX..................XX...X........... 5 iobs/IOU1 ..........X.......X..................... 2 iobs/IOL1 ..........X......X...................... 2 nBERR_FSB .X......X..X..XX........................ 5 IOPWReady ..X.....XX...XX......................... 5 ram/RS_FSM_FFd6 ...XX...X.....X.....X.X....XX........... 8 nBR_IOB .....XXX........X....................... 4 ram/RS_FSM_FFd8 ...XX...X.....X.....X.X..X.XX........... 9 ram/CAS ...XX...X.....X.....X.X...XXX........... 9 ram/RAMEN ...XX...X.....X.....XXX..X.XX........... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0'); ALE0M_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND nAoutOE) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/IOS_FSM_FFd1) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/IOS_FSM_FFd2) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M) OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IORDREQr AND NOT iobm/IOWRREQr)); FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0'); C20MEN <= '0'; C25MEN <= '1'; FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0'); IOACT_D <= ((iobm/IOS_FSM_FFd4) OR (iobm/IOS_FSM_FFd5) OR (iobm/IOS_FSM_FFd6) OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3) OR (iobm/IOS_FSM_FFd7 AND iobm/IOWRREQr AND NOT nAoutOE) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND IOACT AND NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2) OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr) OR (iobm/IOS_FSM_FFd7 AND iobm/IORDREQr AND NOT nAoutOE)); FDCPE_IOBERR: FDCPE port map (IOBERR,NOT nBERR_IOB,NOT C8M,nAS_IOB,'0'); FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,NOT C8M,nAS_IOB,'0'); IODONE_D <= ((NOT nRES.PIN) OR (NOT nDTACK_IOB) OR (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND iobm/ES(3))); FTCPE_IOL0: FTCPE port map (IOL0,IOL0_T,FCLK,'0','0'); IOL0_T <= ((iobs/TS_FSM_FFd1) OR (iobs/IOL1 AND IOL0 AND NOT nADoutLE1) OR (NOT iobs/IOL1 AND NOT IOL0 AND NOT nADoutLE1) OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (nLDS_FSB AND NOT IOL0 AND nADoutLE1) OR (NOT nLDS_FSB AND IOL0 AND nADoutLE1)); FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0'); IONPReady_D <= ((nAS_FSB AND NOT fsb/ASrf) OR (NOT iobs/Sent AND NOT IONPReady) OR (NOT IONPReady AND NOT iobs/IODONEr(0)) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nWE_FSB AND NOT IONPReady)); FDCPE_IOPWReady: FDCPE port map (IOPWReady,IOPWReady_D,FCLK,'0','0'); IOPWReady_D <= ((nAS_FSB AND NOT fsb/ASrf) OR (NOT IOPWReady AND NOT iobs/Clear1 AND NOT nADoutLE1)); FDCPE_IORDREQ: FDCPE port map (IORDREQ,IORDREQ_D,FCLK,'0','0'); IORDREQ_D <= ((NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1) OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr) OR (iobs/TS_FSM_FFd2 AND NOT IORDREQ) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)); FTCPE_IOU0: FTCPE port map (IOU0,IOU0_T,FCLK,'0','0'); IOU0_T <= ((iobs/TS_FSM_FFd1) OR (NOT iobs/IOU1 AND NOT IOU0 AND NOT nADoutLE1) OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (nUDS_FSB AND NOT IOU0 AND nADoutLE1) OR (NOT nUDS_FSB AND IOU0 AND nADoutLE1) OR (iobs/IOU1 AND IOU0 AND NOT nADoutLE1)); FDCPE_IOWRREQ: FDCPE port map (IOWRREQ,IOWRREQ_D,FCLK,'0','0'); IOWRREQ_D <= ((iobs/IORW1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1) OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr) OR (iobs/TS_FSM_FFd2 AND NOT IOWRREQ) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)); RA(0) <= A_FSB(9); RA(1) <= A_FSB(10); RA(2) <= A_FSB(16); RA(3) <= A_FSB(19); RA(4) <= A_FSB(11); RA(5) <= A_FSB(12); RA(6) <= A_FSB(13); RA(7) <= A_FSB(14); RA(8) <= A_FSB(18); RA(9) <= A_FSB(15); RA(10) <= A_FSB(17); RA(11) <= A_FSB(19); FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE); RefReq_D <= (NOT RefUrg AND NOT cnt/Timer(1) AND NOT cnt/Timer(2)); RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_RefUrg: FTCPE port map (RefUrg,RefUrg_T,FCLK,'0','0',RefUrg_CE); RefUrg_T <= ((RefUrg AND cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)) OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND NOT cnt/TimerTC) OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND cnt/Er(0)) OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND NOT cnt/Er(1))); RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1)); FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0'); FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0'); FTCPE_cnt/INITS_FSM_FFd1: FTCPE port map (cnt/INITS_FSM_FFd1,cnt/INITS_FSM_FFd1_T,FCLK,'0','0'); cnt/INITS_FSM_FFd1_T <= (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/INITS_FSM_FFd1 AND cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/nIPL2r AND cnt/Er(1)); FTCPE_cnt/INITS_FSM_FFd2: FTCPE port map (cnt/INITS_FSM_FFd2,cnt/INITS_FSM_FFd2_T,FCLK,'0','0'); cnt/INITS_FSM_FFd2_T <= ((cnt/TimerTC AND cnt/LTimerTC AND cnt/INITS_FSM_FFd1 AND cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)) OR (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1))); FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/LTimer_CE(0)); cnt/LTimer_CE(0) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/LTimer_CE(1)); cnt/LTimer_CE(1) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/LTimer_CE(2)); cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1)); cnt/LTimer_CE(2) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/LTimer_CE(3)); cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2)); cnt/LTimer_CE(3) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/LTimer_CE(4)); cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3)); cnt/LTimer_CE(4) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/LTimer_CE(5)); cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4)); cnt/LTimer_CE(5) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/LTimer_CE(6)); cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5)); cnt/LTimer_CE(6) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/LTimer_CE(7)); cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6)); cnt/LTimer_CE(7) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/LTimer_CE(8)); cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7)); cnt/LTimer_CE(8) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/LTimer_CE(9)); cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8)); cnt/LTimer_CE(9) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/LTimer_CE(10)); cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9)); cnt/LTimer_CE(10) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/LTimer_CE(11)); cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9)); cnt/LTimer_CE(11) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/LTimer12: FTCPE port map (cnt/LTimer(12),cnt/LTimer_T(12),FCLK,'0','0',cnt/LTimer_CE(12)); cnt/LTimer_T(12) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(11) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9)); cnt/LTimer_CE(12) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FDCPE_cnt/LTimerTC: FDCPE port map (cnt/LTimerTC,cnt/LTimerTC_D,FCLK,'0','0',cnt/LTimerTC_CE); cnt/LTimerTC_D <= (NOT cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(11) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND cnt/LTimer(12)); cnt/LTimerTC_CE <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0)); cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)); cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1)); FDCPE_cnt/Timer1: FDCPE port map (cnt/Timer(1),cnt/Timer_D(1),FCLK,'0','0',cnt/Timer_CE(1)); cnt/Timer_D(1) <= ((cnt/Timer(0) AND cnt/Timer(1)) OR (NOT cnt/Timer(0) AND NOT cnt/Timer(1)) OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1))); cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1)); FDCPE_cnt/Timer2: FDCPE port map (cnt/Timer(2),cnt/Timer_D(2),FCLK,'0','0',cnt/Timer_CE(2)); cnt/Timer_D(2) <= ((NOT cnt/Timer(0) AND NOT cnt/Timer(2)) OR (NOT cnt/Timer(1) AND NOT cnt/Timer(2)) OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2)) OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1))); cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1)); FDCPE_cnt/TimerTC: FDCPE port map (cnt/TimerTC,cnt/TimerTC_D,FCLK,'0','0',cnt/TimerTC_CE); cnt/TimerTC_D <= (RefUrg AND cnt/Timer(0) AND NOT cnt/Timer(1) AND NOT cnt/Timer(2)); cnt/TimerTC_CE <= (NOT cnt/Er(0) AND cnt/Er(1)); FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0'); FDCPE_cs/ODCSr: FDCPE port map (cs/ODCSr,cs/ODCSr_D,FCLK,'0','0'); cs/ODCSr_D <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT nAS_FSB) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND fsb/ASrf)); FTCPE_cs/nOverlay: FTCPE port map (cs/nOverlay,cs/nOverlay_T,FCLK,'0','0'); cs/nOverlay_T <= ((NOT nRES.PIN AND cs/nOverlay AND nAS_FSB AND NOT fsb/ASrf) OR (nRES.PIN AND NOT cs/nOverlay AND nAS_FSB AND cs/ODCSr AND NOT fsb/ASrf)); FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0'); FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0'); FTCPE_iobm/DoutOE: FTCPE port map (iobm/DoutOE,iobm/DoutOE_T,C16M,'0','0'); iobm/DoutOE_T <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND NOT iobm/DoutOE AND iobm/IOWRREQr) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/DoutOE) OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/DoutOE) OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/DoutOE AND NOT iobm/IOWRREQr)); FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0'); iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er) OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3) AND E) OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3) AND NOT iobm/Er)); FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0'); iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1)) OR (NOT iobm/ES(0) AND NOT iobm/ES(1)) OR (NOT E AND iobm/Er) OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3))); FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0'); iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E) OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er) OR (iobm/ES(2) AND NOT E AND iobm/Er)); FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0'); iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er) OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND E) OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND NOT iobm/Er) OR (iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND iobm/ES(3))); FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0'); FDCPE_iobm/IORDREQr: FDCPE port map (iobm/IORDREQr,IORDREQ,C16M,'0','0'); FDCPE_iobm/IOS0: FDCPE port map (iobm/IOS0,iobm/IOS0_D,C16M,'0','0'); iobm/IOS0_D <= ((iobm/IOS_FSM_FFd1) OR (iobm/IOS_FSM_FFd7 AND iobm/C8Mr) OR (iobm/IOS_FSM_FFd7 AND nAoutOE) OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IORDREQr AND NOT iobm/IOWRREQr) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd2 AND iobm/IOS0)); FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0'); FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0'); iobm/IOS_FSM_FFd2_D <= ((IOBERR AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr) OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)); FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0'); iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd4) OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr) OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3)); FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0'); FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0'); FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0'); iobm/IOS_FSM_FFd6_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IORDREQr AND NOT nAoutOE) OR (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOWRREQr AND NOT nAoutOE)); FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0'); iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1) OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IORDREQr AND NOT nAoutOE) OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IOWRREQr AND NOT nAoutOE)); FDCPE_iobm/IOWRREQr: FDCPE port map (iobm/IOWRREQr,IOWRREQ,C16M,'0','0'); FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0'); FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0'); iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2); FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0'); FDCPE_iobs/IODONEr0: FDCPE port map (iobs/IODONEr(0),IODONE,FCLK,'0','0'); FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1); FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0'); iobs/IORW1_T <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND nADoutLE1) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)); FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1); FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0'); iobs/Load1_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND nADoutLE1) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)); FDCPE_iobs/Sent: FDCPE port map (iobs/Sent,iobs/Sent_D,FCLK,'0','0'); iobs/Sent_D <= ((A_FSB(23) AND NOT iobs/Sent AND iobs/TS_FSM_FFd2) OR (A_FSB(22) AND NOT iobs/Sent AND iobs/TS_FSM_FFd2) OR (NOT iobs/Sent AND nWE_FSB AND iobs/TS_FSM_FFd1) OR (NOT iobs/Sent AND nWE_FSB AND iobs/TS_FSM_FFd2) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT iobs/Sent AND cs/nOverlay) OR (NOT iobs/Sent AND NOT nADoutLE1) OR (nAS_FSB AND NOT fsb/ASrf) OR (A_FSB(23) AND NOT iobs/Sent AND iobs/TS_FSM_FFd1) OR (A_FSB(22) AND NOT iobs/Sent AND iobs/TS_FSM_FFd1)); FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0'); iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)); FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0'); iobs/TS_FSM_FFd2_D <= ((nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)); nADoutLE0 <= (NOT ALE0M AND NOT ALE0S); FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0'); nADoutLE1_D <= ((iobs/Load1) OR (NOT iobs/Clear1 AND NOT nADoutLE1)); FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0'); nAS_IOB <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IORDREQr AND NOT iobm/IOWRREQr)); nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z'; nAS_IOB_OE <= NOT nAoutOE; FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0'); nAoutOE_D <= ((NOT nBR_IOB AND cnt/INITS_FSM_FFd1 AND cnt/INITS_FSM_FFd2) OR (cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2 AND NOT nAoutOE)); FDCPE_nBERR_FSB: FDCPE port map (nBERR_FSB,nBERR_FSB_D,FCLK,'0','0'); nBERR_FSB_D <= ((NOT iobs/Sent AND nBERR_FSB) OR (NOT IOBERR AND nBERR_FSB) OR (nAS_FSB AND NOT fsb/ASrf)); FTCPE_nBR_IOB: FTCPE port map (nBR_IOB,nBR_IOB_T,FCLK,'0','0'); nBR_IOB_T <= ((nBR_IOB AND NOT cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2) OR (NOT nBR_IOB AND NOT cnt/INITS_FSM_FFd1 AND cnt/INITS_FSM_FFd2 AND NOT cnt/nIPL2r)); FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/CAS,NOT FCLK,'0','0'); FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0'); nDTACK_FSB_D <= ((NOT A_FSB(22) AND NOT IONPReady AND NOT IOPWReady) OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18)) OR (A_FSB(23) AND NOT IONPReady) OR (nAS_FSB AND NOT fsb/ASrf) OR (A_FSB(22) AND A_FSB(21) AND NOT IONPReady) OR (A_FSB(22) AND A_FSB(20) AND NOT IONPReady) OR (NOT A_FSB(22) AND nWE_FSB AND NOT IONPReady)); FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0'); nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4); nDinOE <= NOT (((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB) OR (A_FSB(21) AND nWE_FSB AND NOT nAS_FSB) OR (A_FSB(20) AND nWE_FSB AND NOT nAS_FSB) OR (NOT A_FSB(22) AND cs/nOverlay AND nWE_FSB AND NOT nAS_FSB))); nDoutOE <= NOT (((iobm/DoutOE AND NOT nAoutOE) OR (NOT iobm/IORDREQr AND iobm/IOS0 AND NOT iobm/IOWRREQr AND NOT nAoutOE))); FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0'); nLDS_IOB <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOL0 AND iobm/IORDREQr) OR (iobm/IOS_FSM_FFd3 AND IOL0) OR (iobm/IOS_FSM_FFd4 AND IOL0) OR (iobm/IOS_FSM_FFd5 AND IOL0) OR (NOT nLDS_IOB AND iobm/IOS_FSM_FFd6 AND IOL0)); nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z'; nLDS_IOB_OE <= NOT nAoutOE; nOE <= NOT ((nWE_FSB AND NOT nAS_FSB)); nRAMLWE <= NOT ((ram/RAMEN AND NOT nWE_FSB AND NOT nLDS_FSB AND NOT nAS_FSB)); nRAMUWE <= NOT ((ram/RAMEN AND NOT nWE_FSB AND NOT nUDS_FSB AND NOT nAS_FSB)); FDCPE_nRAS: FDCPE port map (nRAS,nRAS_D,FCLK,'0','0'); nRAS_D <= (NOT ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd6); nRES_I <= '0'; nRES <= nRES_I when nRES_OE = '1' else 'Z'; nRES_OE <= NOT nRESout; FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0'); nRESout_D <= (cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2); nROMCS <= NOT (((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20)) OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT cs/nOverlay))); nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB)); FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0'); nUDS_IOB <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOU0 AND iobm/IORDREQr) OR (iobm/IOS_FSM_FFd3 AND IOU0) OR (iobm/IOS_FSM_FFd4 AND IOU0) OR (iobm/IOS_FSM_FFd5 AND IOU0) OR (NOT nUDS_IOB AND iobm/IOS_FSM_FFd6 AND IOU0)); nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z'; nUDS_IOB_OE <= NOT nAoutOE; FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C8M,'0','0'); nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3)) OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3) AND IOACT AND iobm/VPAr)); nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z'; nVMA_IOB_OE <= NOT nAoutOE; FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB); nVPA_FSB_D <= ((A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND IONPReady AND NOT nAS_FSB) OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND IONPReady AND fsb/ASrf)); FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,FCLK,'0','0'); ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf); FDCPE_ram/CAS: FDCPE port map (ram/CAS,ram/CAS_D,FCLK,'0','0'); ram/CAS_D <= ((ram/RS_FSM_FFd6) OR (RefUrg AND NOT ram/RAMEN AND NOT ram/RefDone AND ram/RS_FSM_FFd8) OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND ram/RS_FSM_FFd8 AND NOT fsb/ASrf) OR (RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd8 AND NOT ram/BACTr) OR (RefReq AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND fsb/ASrf AND NOT ram/BACTr)); FDCPE_ram/Once: FDCPE port map (ram/Once,ram/Once_D,FCLK,'0','0',ram/Once_CE); ram/Once_D <= (nAS_FSB AND NOT fsb/ASrf); ram/Once_CE <= (nAS_FSB AND NOT fsb/ASrf); FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0'); ram/RAMEN_D <= ((RefUrg AND NOT ram/RefDone AND nAS_FSB AND ram/RS_FSM_FFd8 AND NOT fsb/ASrf) OR (RefReq AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND fsb/ASrf AND NOT ram/BACTr) OR (NOT ram/RAMEN AND NOT nAS_FSB AND ram/Once) OR (NOT ram/RAMEN AND NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4) OR (NOT ram/RAMEN AND ram/Once AND fsb/ASrf) OR (RefUrg AND NOT ram/RAMEN AND NOT ram/RefDone AND ram/RS_FSM_FFd8) OR (RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd8 AND NOT ram/BACTr)); FDCPE_ram/RS_FSM_FFd1: FDCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd2,FCLK,'0','0'); FDCPE_ram/RS_FSM_FFd2: FDCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd3,FCLK,'0','0'); FDCPE_ram/RS_FSM_FFd3: FDCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd6,FCLK,'0','0'); FDCPE_ram/RS_FSM_FFd4: FDCPE port map (ram/RS_FSM_FFd4,ram/RS_FSM_FFd1,FCLK,'0','0'); FDCPE_ram/RS_FSM_FFd6: FDCPE port map (ram/RS_FSM_FFd6,ram/RS_FSM_FFd6_D,FCLK,'0','0'); ram/RS_FSM_FFd6_D <= ((RefUrg AND NOT ram/RAMEN AND NOT ram/RefDone AND ram/RS_FSM_FFd8) OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND ram/RS_FSM_FFd8 AND NOT fsb/ASrf) OR (RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd8 AND NOT ram/BACTr) OR (RefReq AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND fsb/ASrf AND NOT ram/BACTr)); FDCPE_ram/RS_FSM_FFd8: FDCPE port map (ram/RS_FSM_FFd8,ram/RS_FSM_FFd8_D,FCLK,'0','0'); ram/RS_FSM_FFd8_D <= ((NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4) OR (RefUrg AND NOT ram/RAMEN AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd4) OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd4 AND NOT fsb/ASrf) OR (RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd4 AND NOT ram/BACTr) OR (RefReq AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd4 AND fsb/ASrf AND NOT ram/BACTr)); FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0'); ram/RefDone_D <= ((NOT RefUrg AND NOT RefReq) OR (NOT ram/RefDone AND NOT ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd2)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 KPR 51 VCC 2 KPR 52 RA<7> 3 KPR 53 RA<0> 4 KPR 54 RA<8> 5 VCC 55 RA<10> 6 KPR 56 RA<9> 7 A_FSB<9> 57 VCC 8 A_FSB<10> 58 C25MEN 9 A_FSB<11> 59 C20MEN 10 A_FSB<12> 60 KPR 11 A_FSB<13> 61 KPR 12 A_FSB<14> 62 GND 13 A_FSB<15> 63 RA<11> 14 A_FSB<16> 64 nRAS 15 A_FSB<17> 65 nRAMLWE 16 A_FSB<18> 66 nRAMUWE 17 A_FSB<19> 67 KPR 18 A_FSB<20> 68 KPR 19 A_FSB<21> 69 GND 20 A_FSB<22> 70 nBERR_FSB 21 GND 71 KPR 22 C16M 72 nBR_IOB 23 C8M 73 KPR 24 A_FSB<23> 74 nVMA_IOB 25 E 75 GND 26 VCC 76 nBERR_IOB 27 FCLK 77 nVPA_IOB 28 nDTACK_FSB 78 nDTACK_IOB 29 nWE_FSB 79 nLDS_IOB 30 nLDS_FSB 80 nUDS_IOB 31 GND 81 nAS_IOB 32 nAS_FSB 82 nADoutLE1 33 nUDS_FSB 83 TDO 34 nROMWE 84 GND 35 nROMCS 85 nADoutLE0 36 nCAS 86 nDinLE 37 nOE 87 nAoutOE 38 VCC 88 VCC 39 KPR 89 nDoutOE 40 RA<4> 90 nDinOE 41 RA<3> 91 nRES 42 RA<5> 92 nIPL2 43 RA<2> 93 nVPA_FSB 44 GND 94 KPR 45 TDI 95 KPR 46 RA<6> 96 KPR 47 TMS 97 KPR 48 TCK 98 VCC 49 KPR 99 KPR 50 RA<1> 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25