Timing Report

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Design Name WarpSE
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Wed Oct 09 07:59:47 2024
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 11.400 ns.
Max. Clock Frequency (fSYSTEM) 87.719 MHz.
Limited by Cycle Time for FCLK
Clock to Setup (tCYC) 11.400 ns.
Pad to Pad Delay (tPD) 15.500 ns.
Setup to Clock at the Pad (tSU) 7.900 ns.
Clock Pad to Output Pad Delay (tCO) 19.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 11.4 467 467
AUTO_TS_P2P 0.0 19.0 93 93
AUTO_TS_P2F 0.0 9.7 154 154
AUTO_TS_F2P 0.0 17.2 44 44


Constraint: TS1000

Description: PERIOD:PERIOD_FCLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_C16M:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_C8M:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
QoSEN.Q to iobs/TS_FSM_FFd2.D 0.000 11.400 -11.400
iobs/TS_FSM_FFd2.Q to iobs/TS_FSM_FFd2.D 0.000 11.400 -11.400
nADoutLE1.Q to iobs/TS_FSM_FFd2.D 0.000 11.400 -11.400


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
FCLK to nROMOE 0.000 19.000 -19.000
C16M to nADoutLE0 0.000 18.000 -18.000
FCLK to nADoutLE0 0.000 18.000 -18.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A_FSB<19> to iobs/TS_FSM_FFd2.D 0.000 9.700 -9.700
A_FSB<20> to iobs/TS_FSM_FFd2.D 0.000 9.700 -9.700
A_FSB<21> to iobs/TS_FSM_FFd2.D 0.000 9.700 -9.700


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
cs/Overlay.Q to nROMOE 0.000 17.200 -17.200
ALE0M.Q to nADoutLE0 0.000 16.200 -16.200
ALE0S.Q to nADoutLE0 0.000 16.200 -16.200



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
FCLK 87.719 Limited by Cycle Time for FCLK
C16M 90.909 Limited by Cycle Time for C16M
C8M 100.000 Limited by Cycle Time for C8M

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FCLK
Source Pad Setup to clk (edge) Hold to clk (edge)
A_FSB<10> 7.500 0.000
A_FSB<11> 7.500 0.000
A_FSB<12> 7.500 0.000
A_FSB<13> 7.500 0.000
A_FSB<14> 7.500 0.000
A_FSB<15> 7.500 0.000
A_FSB<16> 7.500 0.000
A_FSB<17> 7.500 0.000
A_FSB<18> 7.500 0.000
A_FSB<19> 7.900 0.000
A_FSB<20> 7.900 0.000
A_FSB<21> 7.900 0.000
A_FSB<22> 7.900 0.000
A_FSB<23> 7.900 0.000
A_FSB<8> 7.500 0.000
A_FSB<9> 7.500 0.000
C8M 6.500 0.000
E 6.500 0.000
nAS_FSB 7.500 0.000
nBERR_IOB 6.500 0.000
nIPL2 6.500 0.000
nLDS_FSB 6.500 0.000
nRES 7.500 0.000
nUDS_FSB 6.500 0.000
nWE_FSB 7.900 0.000

Setup/Hold Times for Clock C16M
Source Pad Setup to clk (edge) Hold to clk (edge)
C8M 6.500 0.000
nBERR_IOB 7.500 0.000
nDTACK_IOB 6.500 0.000
nRES 6.500 0.000

Setup/Hold Times for Clock C8M
Source Pad Setup to clk (edge) Hold to clk (edge)
E 6.500 0.000
nVPA_IOB 6.500 0.000


Clock to Pad Timing

Clock FCLK to Pad
Destination Pad Clock (edge) to Pad
nROMOE 19.000
nADoutLE0 18.000
nDinOE 18.000
nRAMLWE 18.000
nRAMUWE 18.000
RA<11> 14.500
RnW_IOB 14.500
nAS_IOB 14.500
nBR_IOB 14.500
nLDS_IOB 14.500
nRES 14.500
nUDS_IOB 14.500
nVMA_IOB 14.500
RA<0> 13.500
RA<10> 13.500
RA<1> 13.500
RA<2> 13.500
RA<3> 13.500
RA<4> 13.500
RA<5> 13.500
RA<6> 13.500
RA<7> 13.500
RA<8> 13.500
RA<9> 13.500
nDoutOE 13.500
nRAS 13.500
nAoutOE 10.300
nBERR_FSB 10.300
nDTACK_FSB 10.300
nOE 10.300
nVPA_FSB 10.300
MCKE 5.800
nADoutLE1 5.800
nCAS 5.800

Clock C16M to Pad
Destination Pad Clock (edge) to Pad
nADoutLE0 18.000
nDoutOE 13.500
RnW_IOB 10.300
nAS_IOB 10.300
nLDS_IOB 10.300
nUDS_IOB 10.300
nDinLE 5.800

Clock C8M to Pad
Destination Pad Clock (edge) to Pad
nVMA_IOB 10.300


Clock to Setup Times for Clocks

Clock to Setup for clock FCLK
Source Destination Delay
QoSEN.Q iobs/TS_FSM_FFd2.D 11.400
iobs/TS_FSM_FFd2.Q iobs/TS_FSM_FFd2.D 11.400
nADoutLE1.Q iobs/TS_FSM_FFd2.D 11.400
ASrf.Q IONPReady.D 11.000
ASrf.Q RAMReady.D 11.000
ASrf.Q cnt/QoSCSr.D 11.000
ASrf.Q cnt/SndQoSCSr.D 11.000
ASrf.Q iobs/IORW1.D 11.000
ASrf.Q iobs/Sent.D 11.000
ASrf.Q iobs/TS_FSM_FFd2.D 11.000
ASrf.Q ram/RASEN.D 11.000
ASrf.Q ram/RS<0>.D 11.000
ASrf.Q ram/RS<2>.D 11.000
ASrf.Q ram/RefCAS.D 11.000
BACTr.Q ram/RASEN.D 11.000
BACTr.Q ram/RS<2>.D 11.000
BACTr.Q ram/RefCAS.D 11.000
IONPReady.Q IONPReady.D 11.000
IONPReady.Q nDTACK_FSB.D 11.000
QoSEN.Q IOREQ.D 11.000
QoSEN.Q iobs/IORW1.D 11.000
QoSEN.Q iobs/Sent.D 11.000
RAMReady.Q nDTACK_FSB.D 11.000
RefReq.Q ram/RASEN.D 11.000
RefReq.Q ram/RS<2>.D 11.000
RefReq.Q ram/RefCAS.D 11.000
RefReq.Q ram/RefDone.D 11.000
RefUrg.Q RAMReady.D 11.000
RefUrg.Q ram/RASEN.D 11.000
RefUrg.Q ram/RS<2>.D 11.000
cs/Overlay.Q ram/RS<0>.D 11.000
iobs/IODONEr<0>.Q IONPReady.D 11.000
iobs/IORW1.Q iobs/IORW1.D 11.000
iobs/Sent.Q IONPReady.D 11.000
iobs/Sent.Q iobs/IORW1.D 11.000
iobs/Sent.Q iobs/Sent.D 11.000
iobs/Sent.Q nDTACK_FSB.D 11.000
iobs/TS_FSM_FFd1.Q iobs/IORW1.D 11.000
iobs/TS_FSM_FFd1.Q iobs/Sent.D 11.000
iobs/TS_FSM_FFd2.Q IOREQ.D 11.000
iobs/TS_FSM_FFd2.Q iobs/IORW1.D 11.000
iobs/TS_FSM_FFd2.Q iobs/Sent.D 11.000
nADoutLE1.Q IOREQ.D 11.000
nADoutLE1.Q iobs/IORW1.D 11.000
nADoutLE1.Q iobs/Sent.D 11.000
nADoutLE1.Q nDTACK_FSB.D 11.000
ram/RASEN.Q ram/RS<0>.D 11.000
ram/RS<0>.Q RAMReady.D 11.000
ram/RS<0>.Q ram/RASEN.D 11.000
ram/RS<0>.Q ram/RS<0>.D 11.000
ram/RS<0>.Q ram/RS<2>.D 11.000
ram/RS<0>.Q ram/RefCAS.D 11.000
ram/RS<1>.Q RAMReady.D 11.000
ram/RS<1>.Q ram/RASEN.D 11.000
ram/RS<1>.Q ram/RS<2>.D 11.000
ram/RS<1>.Q ram/RefCAS.D 11.000
ram/RS<2>.Q RAMReady.D 11.000
ram/RS<2>.Q ram/RASEN.D 11.000
ram/RS<2>.Q ram/RS<2>.D 11.000
ram/RS<2>.Q ram/RefCAS.D 11.000
ram/RS<2>.Q ram/RefDone.D 11.000
ram/RefDone.Q ram/RS<2>.D 11.000
ram/RefDone.Q ram/RefCAS.D 11.000
ASrf.Q BACTr.D 10.000
ASrf.Q IOREQ.D 10.000
ASrf.Q MCKE.D 10.000
ASrf.Q QoSEN.CE 10.000
ASrf.Q cs/Overlay.D 10.000
ASrf.Q iobs/Load1.D 10.000
ASrf.Q nBERR_FSB.D 10.000
ASrf.Q ram/RASEL.D 10.000
ASrf.Q ram/RS<1>.D 10.000
BACTr.Q RAMReady.D 10.000
IOL0.Q IOL0.D 10.000
IONPReady.Q nVPA_FSB.D 10.000
IOU0.Q IOU0.D 10.000
QoSEN.Q IONPReady.D 10.000
QoSEN.Q MCKE.D 10.000
QoSEN.Q iobs/Load1.D 10.000
QoSEN.Q nDTACK_FSB.D 10.000
RefReq.Q RAMReady.D 10.000
RefUrg.Q ram/RefCAS.D 10.000
cnt/C8Mr<0>.Q MCKE.D 10.000
cnt/C8Mr<0>.Q cnt/C8Mr<1>.D 10.000
cnt/C8Mr<0>.Q cnt/nPOR.D 10.000
cnt/C8Mr<1>.Q MCKE.D 10.000
cnt/C8Mr<1>.Q cnt/C8Mr<2>.D 10.000
cnt/C8Mr<1>.Q cnt/nPOR.D 10.000
cnt/C8Mr<2>.Q cnt/C8Mr<3>.D 10.000
cnt/C8Mr<2>.Q cnt/nPOR.D 10.000
cnt/C8Mr<3>.Q cnt/nPOR.D 10.000
cnt/Er<0>.Q RefReq.CE 10.000
cnt/Er<0>.Q RefUrg.CE 10.000
cnt/Er<0>.Q cnt/Er<1>.D 10.000
cnt/Er<0>.Q cnt/Timer<0>.CE 10.000
cnt/Er<0>.Q cnt/Timer<0>.D 10.000
cnt/Er<0>.Q cnt/Timer<1>.CE 10.000
cnt/Er<0>.Q cnt/Timer<1>.D 10.000
cnt/Er<0>.Q cnt/Timer<2>.CE 10.000
cnt/Er<0>.Q cnt/Timer<3>.CE 10.000
cnt/Er<0>.Q cnt/Timer<3>.D 10.000
cnt/Er<0>.Q cnt/TimerTick.D 10.000
cnt/Er<1>.Q RefReq.CE 10.000
cnt/Er<1>.Q RefUrg.CE 10.000
cnt/Er<1>.Q cnt/Timer<0>.CE 10.000
cnt/Er<1>.Q cnt/Timer<0>.D 10.000
cnt/Er<1>.Q cnt/Timer<1>.CE 10.000
cnt/Er<1>.Q cnt/Timer<1>.D 10.000
cnt/Er<1>.Q cnt/Timer<2>.CE 10.000
cnt/Er<1>.Q cnt/Timer<3>.CE 10.000
cnt/Er<1>.Q cnt/Timer<3>.D 10.000
cnt/Er<1>.Q cnt/TimerTick.D 10.000
cnt/IS<0>.Q cnt/IS<0>.D 10.000
cnt/IS<0>.Q cnt/IS<1>.D 10.000
cnt/IS<0>.Q nAoutOE.D 10.000
cnt/IS<0>.Q nBR_IOBout.D 10.000
cnt/IS<0>.Q nRESout.D 10.000
cnt/IS<1>.Q cnt/IS<0>.D 10.000
cnt/IS<1>.Q cnt/IS<1>.D 10.000
cnt/IS<1>.Q nAoutOE.D 10.000
cnt/IS<1>.Q nBR_IOBout.D 10.000
cnt/IS<1>.Q nRESout.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<1>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<0>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<10>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<10>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<11>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<1>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<2>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<3>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<4>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<5>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<6>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<7>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<8>.Q cnt/LTimerTick.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<9>.Q cnt/LTimerTick.D 10.000
cnt/LTimerTick.Q cnt/IS<0>.D 10.000
cnt/LTimerTick.Q cnt/IS<1>.D 10.000
cnt/LTimerTick.Q nRESout.D 10.000
cnt/QS<0>.Q QoSEN.D 10.000
cnt/QS<0>.Q cnt/QS<0>.D 10.000
cnt/QS<0>.Q cnt/QS<1>.D 10.000
cnt/QS<0>.Q cnt/QS<2>.D 10.000
cnt/QS<0>.Q cnt/QS<3>.D 10.000
cnt/QS<1>.Q QoSEN.D 10.000
cnt/QS<1>.Q cnt/QS<0>.D 10.000
cnt/QS<1>.Q cnt/QS<1>.D 10.000
cnt/QS<1>.Q cnt/QS<2>.D 10.000
cnt/QS<1>.Q cnt/QS<3>.D 10.000
cnt/QS<2>.Q QoSEN.D 10.000
cnt/QS<2>.Q cnt/QS<0>.D 10.000
cnt/QS<2>.Q cnt/QS<1>.D 10.000
cnt/QS<2>.Q cnt/QS<2>.D 10.000
cnt/QS<2>.Q cnt/QS<3>.D 10.000
cnt/QS<3>.Q QoSEN.D 10.000
cnt/QS<3>.Q cnt/QS<0>.D 10.000
cnt/QS<3>.Q cnt/QS<1>.D 10.000
cnt/QS<3>.Q cnt/QS<2>.D 10.000
cnt/QS<3>.Q cnt/QS<3>.D 10.000
cnt/QoSCSr.Q cnt/QS<0>.D 10.000
cnt/QoSCSr.Q cnt/QS<1>.D 10.000
cnt/QoSCSr.Q cnt/QS<2>.D 10.000
cnt/QoSCSr.Q cnt/QS<3>.D 10.000
cnt/SndQoSCSr.Q cnt/QS<0>.D 10.000
cnt/SndQoSCSr.Q cnt/QS<1>.D 10.000
cnt/SndQoSCSr.Q cnt/QS<2>.D 10.000
cnt/SndQoSCSr.Q cnt/QS<3>.D 10.000
cnt/Timer<0>.Q RefReq.D 10.000
cnt/Timer<0>.Q cnt/Timer<0>.D 10.000
cnt/Timer<0>.Q cnt/Timer<1>.D 10.000
cnt/Timer<0>.Q cnt/Timer<2>.D 10.000
cnt/Timer<0>.Q cnt/Timer<3>.D 10.000
cnt/Timer<0>.Q cnt/TimerTick.D 10.000
cnt/Timer<1>.Q RefReq.D 10.000
cnt/Timer<1>.Q RefUrg.D 10.000
cnt/Timer<1>.Q cnt/Timer<0>.D 10.000
cnt/Timer<1>.Q cnt/Timer<1>.D 10.000
cnt/Timer<1>.Q cnt/Timer<2>.D 10.000
cnt/Timer<1>.Q cnt/Timer<3>.D 10.000
cnt/Timer<1>.Q cnt/TimerTick.D 10.000
cnt/Timer<2>.Q RefReq.D 10.000
cnt/Timer<2>.Q RefUrg.D 10.000
cnt/Timer<2>.Q cnt/Timer<0>.D 10.000
cnt/Timer<2>.Q cnt/Timer<1>.D 10.000
cnt/Timer<2>.Q cnt/Timer<3>.D 10.000
cnt/Timer<2>.Q cnt/TimerTick.D 10.000
cnt/Timer<3>.Q RefReq.D 10.000
cnt/Timer<3>.Q RefUrg.D 10.000
cnt/Timer<3>.Q cnt/Timer<0>.D 10.000
cnt/Timer<3>.Q cnt/Timer<1>.D 10.000
cnt/Timer<3>.Q cnt/Timer<3>.D 10.000
cnt/Timer<3>.Q cnt/TimerTick.D 10.000
cnt/TimerTick.Q cnt/LTimer<0>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<10>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<11>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<1>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<2>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<3>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<4>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<5>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<6>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<7>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<8>.CE 10.000
cnt/TimerTick.Q cnt/LTimer<9>.CE 10.000
cnt/TimerTick.Q cnt/LTimerTick.D 10.000
cnt/TimerTick.Q cnt/QS<0>.D 10.000
cnt/TimerTick.Q cnt/QS<1>.D 10.000
cnt/TimerTick.Q cnt/QS<2>.D 10.000
cnt/TimerTick.Q cnt/QS<3>.D 10.000
cnt/nPOR.Q cnt/IS<0>.D 10.000
cnt/nPOR.Q cnt/IS<1>.D 10.000
cnt/nPOR.Q cnt/nPOR.D 10.000
cs/Overlay.Q cs/Overlay.D 10.000
cs/Overlay.Q nOE.D 10.000
cs/Overlay.Q ram/RASEL.D 10.000
iobs/Clear1.Q nADoutLE1.D 10.000
iobs/IOACTr.Q IOREQ.D 10.000
iobs/IOACTr.Q iobs/TS_FSM_FFd1.D 10.000
iobs/IOACTr.Q iobs/TS_FSM_FFd2.D 10.000
iobs/IODONEr<0>.Q iobs/IODONEr<1>.D 10.000
iobs/IODONEr<0>.Q nBERR_FSB.D 10.000
iobs/IODONEr<1>.Q IONPReady.D 10.000
iobs/IODONEr<1>.Q nBERR_FSB.D 10.000
iobs/IODONErf.Q iobs/IODONEr<0>.D 10.000
iobs/IOL1.Q IOL0.D 10.000
iobs/IORW1.Q IORW.D 10.000
iobs/IOU1.Q IOU0.D 10.000
iobs/Load1.Q iobs/IOL1.CE 10.000
iobs/Load1.Q iobs/IOU1.CE 10.000
iobs/Load1.Q nADoutLE1.D 10.000
iobs/Sent.Q IOREQ.D 10.000
iobs/Sent.Q iobs/Load1.D 10.000
iobs/Sent.Q iobs/TS_FSM_FFd2.D 10.000
iobs/Sent.Q nBERR_FSB.D 10.000
iobs/TS_FSM_FFd1.Q IOL0.D 10.000
iobs/TS_FSM_FFd1.Q IOREQ.D 10.000
iobs/TS_FSM_FFd1.Q IORW.CE 10.000
iobs/TS_FSM_FFd1.Q IOU0.D 10.000
iobs/TS_FSM_FFd1.Q iobs/Clear1.D 10.000
iobs/TS_FSM_FFd1.Q iobs/Load1.D 10.000
iobs/TS_FSM_FFd1.Q iobs/TS_FSM_FFd1.D 10.000
iobs/TS_FSM_FFd1.Q iobs/TS_FSM_FFd2.D 10.000
iobs/TS_FSM_FFd2.Q ALE0S.D 10.000
iobs/TS_FSM_FFd2.Q IORW.CE 10.000
iobs/TS_FSM_FFd2.Q iobs/Clear1.D 10.000
iobs/TS_FSM_FFd2.Q iobs/Load1.D 10.000
iobs/TS_FSM_FFd2.Q iobs/TS_FSM_FFd1.D 10.000
nADoutLE1.Q IOL0.D 10.000
nADoutLE1.Q IORW.D 10.000
nADoutLE1.Q IOU0.D 10.000
nADoutLE1.Q iobs/Load1.D 10.000
nADoutLE1.Q nADoutLE1.D 10.000
nBERR_FSB.Q nBERR_FSB.D 10.000
nBR_IOBout.Q nAoutOE.D 10.000
nBR_IOBout.Q nBR_IOBout.D 10.000
nDTACK_FSB.Q ram/RASEN.D 10.000
nDTACK_FSB.Q ram/RS<0>.D 10.000
nDTACK_FSB.Q ram/RS<1>.D 10.000
nRESout.Q nRESout.D 10.000
ram/RS<0>.Q nCAS.D 10.000
ram/RS<0>.Q ram/CASEndEN.D 10.000
ram/RS<0>.Q ram/RASEL.D 10.000
ram/RS<0>.Q ram/RASrf.D 10.000
ram/RS<0>.Q ram/RS<1>.D 10.000
ram/RS<1>.Q nCAS.D 10.000
ram/RS<1>.Q ram/CASEndEN.D 10.000
ram/RS<1>.Q ram/RASEL.D 10.000
ram/RS<1>.Q ram/RASrf.D 10.000
ram/RS<1>.Q ram/RS<0>.D 10.000
ram/RS<1>.Q ram/RS<1>.D 10.000
ram/RS<2>.Q nCAS.D 10.000
ram/RS<2>.Q ram/CASEndEN.D 10.000
ram/RS<2>.Q ram/RASEL.D 10.000
ram/RS<2>.Q ram/RASrf.D 10.000
ram/RS<2>.Q ram/RS<0>.D 10.000
ram/RS<2>.Q ram/RS<1>.D 10.000
ram/RefDone.Q RAMReady.D 10.000
ram/RefDone.Q ram/RASEN.D 10.000
ram/RefDone.Q ram/RefDone.D 10.000

Clock to Setup for clock C16M
Source Destination Delay
IODONE.Q IOACT.D 11.000
IODONE.Q IODONE.D 11.000
RnW_IOB.Q RnW_IOB.D 11.000
iobm/C8Mr.Q IOACT.D 11.000
iobm/C8Mr.Q IODONE.D 11.000
iobm/C8Mr.Q RnW_IOB.D 11.000
iobm/IOREQr.Q IOACT.D 11.000
iobm/IOS_FSM_FFd2.Q RnW_IOB.D 11.000
iobm/IOS_FSM_FFd3.Q IOACT.D 11.000
iobm/IOS_FSM_FFd3.Q IODONE.D 11.000
iobm/IOS_FSM_FFd3.Q RnW_IOB.D 11.000
iobm/IOS_FSM_FFd3.Q nLDS_IOB.D 11.000
iobm/IOS_FSM_FFd3.Q nUDS_IOB.D 11.000
iobm/IOS_FSM_FFd4.Q IOACT.D 11.000
iobm/IOS_FSM_FFd4.Q RnW_IOB.D 11.000
iobm/IOS_FSM_FFd4.Q nLDS_IOB.D 11.000
iobm/IOS_FSM_FFd4.Q nUDS_IOB.D 11.000
iobm/IOS_FSM_FFd5.Q IOACT.D 11.000
iobm/IOS_FSM_FFd5.Q IODONE.D 11.000
iobm/IOS_FSM_FFd5.Q RnW_IOB.D 11.000
iobm/IOS_FSM_FFd5.Q nLDS_IOB.D 11.000
iobm/IOS_FSM_FFd5.Q nUDS_IOB.D 11.000
iobm/IOS_FSM_FFd6.Q IOACT.D 11.000
iobm/IOS_FSM_FFd6.Q RnW_IOB.D 11.000
iobm/IOS_FSM_FFd6.Q nLDS_IOB.D 11.000
iobm/IOS_FSM_FFd6.Q nUDS_IOB.D 11.000
iobm/IOS_FSM_FFd7.Q IODONE.D 11.000
iobm/IOS_FSM_FFd7.Q nLDS_IOB.D 11.000
iobm/IOS_FSM_FFd7.Q nUDS_IOB.D 11.000
ALE0M.Q ALE0M.D 10.000
IOACT.Q IOACT.D 10.000
IODONE.Q iobm/IOS_FSM_FFd2.D 10.000
IODONE.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/C8Mr.Q iobm/DoutOE.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/C8Mr.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/C8Mr.Q nAS_IOB.D 10.000
iobm/C8Mr.Q nLDS_IOB.D 10.000
iobm/C8Mr.Q nUDS_IOB.D 10.000
iobm/DoutOE.Q iobm/DoutOE.D 10.000
iobm/IOREQr.Q ALE0M.D 10.000
iobm/IOREQr.Q RnW_IOB.D 10.000
iobm/IOREQr.Q iobm/DoutOE.D 10.000
iobm/IOREQr.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/IOREQr.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IOREQr.Q nAS_IOB.D 10.000
iobm/IOREQr.Q nLDS_IOB.D 10.000
iobm/IOREQr.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd1.Q IOACT.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IOS_FSM_FFd2.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd2.Q IOACT.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd3.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd3.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd4.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd4.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd5.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd5.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd5.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd5.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd6.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd6.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd6.Q iobm/IOS_FSM_FFd5.D 10.000
iobm/IOS_FSM_FFd6.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd7.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd7.Q IOACT.D 10.000
iobm/IOS_FSM_FFd7.Q RnW_IOB.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/IOS_FSM_FFd6.D 10.000
iobm/IOS_FSM_FFd7.Q iobm/IOS_FSM_FFd7.D 10.000
iobm/IOS_FSM_FFd7.Q nAS_IOB.D 10.000

Clock to Setup for clock C8M
Source Destination Delay
iobm/ES<0>.Q iobm/ES<0>.D 10.000
iobm/ES<0>.Q iobm/ES<1>.D 10.000
iobm/ES<0>.Q iobm/ES<2>.D 10.000
iobm/ES<0>.Q iobm/ES<3>.D 10.000
iobm/ES<0>.Q nVMA_IOB.D 10.000
iobm/ES<1>.Q iobm/ES<0>.D 10.000
iobm/ES<1>.Q iobm/ES<1>.D 10.000
iobm/ES<1>.Q iobm/ES<2>.D 10.000
iobm/ES<1>.Q iobm/ES<3>.D 10.000
iobm/ES<1>.Q nVMA_IOB.D 10.000
iobm/ES<2>.Q iobm/ES<0>.D 10.000
iobm/ES<2>.Q iobm/ES<1>.D 10.000
iobm/ES<2>.Q iobm/ES<2>.D 10.000
iobm/ES<2>.Q iobm/ES<3>.D 10.000
iobm/ES<2>.Q nVMA_IOB.D 10.000
iobm/ES<3>.Q iobm/ES<0>.D 10.000
iobm/ES<3>.Q iobm/ES<1>.D 10.000
iobm/ES<3>.Q iobm/ES<3>.D 10.000
iobm/ES<3>.Q nVMA_IOB.D 10.000
iobm/Er.Q iobm/ES<0>.D 10.000
iobm/Er.Q iobm/ES<1>.D 10.000
iobm/Er.Q iobm/ES<2>.D 10.000
iobm/Er.Q iobm/ES<3>.D 10.000
iobm/VPAr.Q nVMA_IOB.D 10.000
nVMA_IOB.Q nVMA_IOB.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A_FSB<20> nROMOE 15.500
A_FSB<21> nROMOE 15.500
A_FSB<22> nROMOE 15.500
A_FSB<23> nROMOE 15.500
nAS_FSB nROMOE 15.500
nWE_FSB nROMOE 15.500
A_FSB<20> nDinOE 14.500
A_FSB<20> nROMWE 14.500
A_FSB<21> nDinOE 14.500
A_FSB<21> nROMWE 14.500
A_FSB<22> nDinOE 14.500
A_FSB<22> nROMWE 14.500
A_FSB<23> nDinOE 14.500
A_FSB<23> nROMWE 14.500
nAS_FSB nDinOE 14.500
nAS_FSB nROMWE 14.500
nLDS_FSB nRAMLWE 14.500
nUDS_FSB nRAMUWE 14.500
nWE_FSB nDinOE 14.500
nWE_FSB nRAMLWE 14.500
nWE_FSB nRAMUWE 14.500
nWE_FSB nROMWE 14.500
A_FSB<19> RA<11> 11.000
A_FSB<20> RA<11> 11.000
A_FSB<10> RA<1> 10.000
A_FSB<11> RA<4> 10.000
A_FSB<12> RA<5> 10.000
A_FSB<13> RA<6> 10.000
A_FSB<14> RA<7> 10.000
A_FSB<15> RA<9> 10.000
A_FSB<16> RA<2> 10.000
A_FSB<17> RA<10> 10.000
A_FSB<18> RA<8> 10.000
A_FSB<19> RA<3> 10.000
A_FSB<1> RA<0> 10.000
A_FSB<20> RA<3> 10.000
A_FSB<21> RA<8> 10.000
A_FSB<22> GA<22> 10.000
A_FSB<22> nRAS 10.000
A_FSB<23> GA<23> 10.000
A_FSB<23> nRAS 10.000
A_FSB<2> RA<1> 10.000
A_FSB<3> RA<4> 10.000
A_FSB<4> RA<5> 10.000
A_FSB<5> RA<6> 10.000
A_FSB<6> RA<7> 10.000
A_FSB<7> RA<10> 10.000
A_FSB<7> RA<2> 10.000
A_FSB<8> RA<9> 10.000
A_FSB<9> RA<0> 10.000
nAS_FSB nRAS 10.000



Number of paths analyzed: 758
Number of Timing errors: 758
Analysis Completed: Wed Oct 09 07:59:47 2024