Environment Settings | ||
Environment Variable | xst | ngdbuild |
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
Path | C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt; C:\Xilinx\14.7\ISE_DS\ISE\bin\nt; C:\Xilinx\14.7\ISE_DS\ISE\lib\nt; C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\14.7\ISE_DS\PlanAhead\bin; C:\Xilinx\14.7\ISE_DS\EDK\bin\nt; C:\Xilinx\14.7\ISE_DS\EDK\lib\nt; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin; C:\Xilinx\14.7\ISE_DS\common\bin\nt; C:\Xilinx\14.7\ISE_DS\common\lib\nt; C:\Program Files (x86)\Common Files\Oracle\Java\javapath; C:\ispLEVER_Classic2_0\ispcpld\bin; C:\ispLEVER_Classic2_0\ispFPGA\bin\nt; C:\ispLEVER_Classic2_0\active-hdl\BIN; C:\WinAVR-20100110\bin; C:\WinAVR-20100110\utils\bin; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Windows\System32\OpenSSH\; C:\Program Files\Microchip\xc8\v2.31\bin; C:\Program Files\PuTTY\; C:\Program Files\WinMerge; C:\Program Files\dotnet\; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Users\zanek\AppData\Local\Microsoft\WindowsApps; C:\Users\zanek\AppData\Local\GitHubDesktop\bin; C:\altera\13.0sp1\modelsim_ase\win32aloem; C:\Users\zanek\.dotnet\tools; C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin |
C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt; C:\Xilinx\14.7\ISE_DS\ISE\bin\nt; C:\Xilinx\14.7\ISE_DS\ISE\lib\nt; C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\14.7\ISE_DS\PlanAhead\bin; C:\Xilinx\14.7\ISE_DS\EDK\bin\nt; C:\Xilinx\14.7\ISE_DS\EDK\lib\nt; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin; C:\Xilinx\14.7\ISE_DS\common\bin\nt; C:\Xilinx\14.7\ISE_DS\common\lib\nt; C:\Program Files (x86)\Common Files\Oracle\Java\javapath; C:\ispLEVER_Classic2_0\ispcpld\bin; C:\ispLEVER_Classic2_0\ispFPGA\bin\nt; C:\ispLEVER_Classic2_0\active-hdl\BIN; C:\WinAVR-20100110\bin; C:\WinAVR-20100110\utils\bin; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Windows\System32\OpenSSH\; C:\Program Files\Microchip\xc8\v2.31\bin; C:\Program Files\PuTTY\; C:\Program Files\WinMerge; C:\Program Files\dotnet\; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Users\zanek\AppData\Local\Microsoft\WindowsApps; C:\Users\zanek\AppData\Local\GitHubDesktop\bin; C:\altera\13.0sp1\modelsim_ase\win32aloem; C:\Users\zanek\.dotnet\tools; C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin |
XILINX | C:\Xilinx\14.7\ISE_DS\ISE\ | C:\Xilinx\14.7\ISE_DS\ISE\ |
XILINX_DSP | C:\Xilinx\14.7\ISE_DS\ISE | C:\Xilinx\14.7\ISE_DS\ISE |
XILINX_EDK | C:\Xilinx\14.7\ISE_DS\EDK | C:\Xilinx\14.7\ISE_DS\EDK |
XILINX_PLANAHEAD | C:\Xilinx\14.7\ISE_DS\PlanAhead | C:\Xilinx\14.7\ISE_DS\PlanAhead |
Synthesis Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-ifn | MXSE.prj | ||
-ifmt | mixed | MIXED | |
-ofn | MXSE | ||
-ofmt | NGC | NGC | |
-p | xc9500xl | ||
-top | MXSE | ||
-opt_mode | Optimization Goal | Speed | SPEED |
-opt_level | Optimization Effort | 1 | 1 |
-iuc | Use synthesis Constraints File | NO | NO |
-keep_hierarchy | Keep Hierarchy | Yes | YES |
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized |
-rtlview | Generate RTL Schematic | Yes | NO |
-bus_delimiter | Bus Delimiter | <> | <> |
-verilog2001 | Verilog 2001 | YES | YES |
-fsm_extract | YES | YES | |
-fsm_encoding | Auto | AUTO | |
-safe_implementation | No | NO | |
-resource_sharing | YES | YES | |
-iobuf | YES | YES | |
-equivalent_register_removal | YES | YES |
Translation Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-intstyle | ise | None | |
-dd | _ngo | None | |
-p | xc95144xl-TQ100-10 | None | |
-uc | MXSE.ucf | None |
Operating System Information | ||
Operating System Information | xst | ngdbuild |
CPU Architecture/Speed | Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz | Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz |
Host | ZanePC | ZanePC |
OS Name | Microsoft , 64-bit | Microsoft , 64-bit |
OS Release | major release (build 9200) | major release (build 9200) |