Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.97 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.98 secs
 
--> Reading design: WarpSE.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "WarpSE.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "WarpSE"
Output Format                      : NGC
Target Device                      : XC9500XL CPLDs

---- Source Options
Top Module Name                    : WarpSE
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
Mux Extraction                     : Yes
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Verilog 2001                       : YES

---- Other Options
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../RAM.v" in library work
ERROR:HDLCompilers:28 - "../RAM.v" line 63 'BACTr' has not been declared
ERROR:HDLCompilers:26 - "../RAM.v" line 69 unexpected token: ';'
ERROR:HDLCompilers:26 - "../RAM.v" line 75 unexpected token: 'begin'
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting ';', found ')'
ERROR:HDLCompilers:26 - "../RAM.v" line 76 unexpected token: '<='
Module <RAM> compiled
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting 'endmodule', found '0'
Compiling verilog file "../IOBS.v" in library work
Compiling verilog file "../IOBM.v" in library work
Module <IOBS> compiled
Compiling verilog file "../FSB.v" in library work
Module <IOBM> compiled
ERROR:HDLCompilers:28 - "../FSB.v" line 59 'BERR' has not been declared
Compiling verilog file "../CS.v" in library work
Module <FSB> compiled
Compiling verilog file "../CNT.v" in library work
Module <CS> compiled
ERROR:HDLCompilers:28 - "../CNT.v" line 29 'RefREQ' has not been declared
ERROR:HDLCompilers:28 - "../CNT.v" line 30 'RefREQ' has not been declared
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting ';', found '='
Module <CNT> compiled
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting 'endmodule', found '0'
Compiling verilog file "../WarpSE.v" in library work
Module <WarpSE> compiled
Analysis of file <"WarpSE.prj"> failed.
--> 

Total memory usage is 190552 kilobytes

Number of errors   :   11 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)