| ********** Mapped Logic ********** |
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FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
ALE0M_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/IOS_FSM_FFd2) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/IOS_FSM_FFd1) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M)); |
| FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0'); |
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FDCPE_BACTr: FDCPE port map (BACTr,BACTr_D,FCLK,'0','0');
BACTr_D <= (nAS_FSB AND NOT fsb/ASrf); |
| GA(22) <= A_FSB(22); |
| GA(23) <= A_FSB(23); |
|
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
IOACT_D <= ((iobm/IOS_FSM_FFd4) OR (iobm/IOS_FSM_FFd5) OR (iobm/IOS_FSM_FFd6) OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND IOACT AND NOT iobm/IOS_FSM_FFd1) OR (iobm/IOS_FSM_FFd7 AND iobm/IOREQr) OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)); |
| FDCPE_IOBERR: FDCPE port map (IOBERR,NOT nBERR_IOB,NOT C8M,nAS_IOB,'0'); |
|
FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,NOT C8M,nAS_IOB,'0');
IODONE_D <= ((NOT nRES.PIN) OR (NOT nDTACK_IOB) OR (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND iobm/ES(3))); |
|
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,FCLK,'0','0');
IOL0_D <= ((iobs/TS_FSM_FFd1 AND IOL0) OR (NOT nLDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1) OR (iobs/IOL1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1)); |
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FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
IONPReady_D <= ((nAS_FSB AND NOT fsb/ASrf) OR (NOT iobs/Sent AND NOT IONPReady) OR (NOT IONPReady AND NOT iobs/IODONEr) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT IONPReady AND NOT nWE_FSB)); |
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FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,FCLK,'0','0');
IOREQ_D <= ((NOT A_FSB(21) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(19) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(18) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(17) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(20) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)); |
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FDCPE_IORW: FDCPE port map (IORW,IORW_D,FCLK,'0','0',IORW_CE);
IORW_D <= ((nWE_FSB AND nADoutLE1) OR (iobs/IORW1 AND NOT nADoutLE1)); IORW_CE <= (NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2); |
|
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,FCLK,'0','0');
IOU0_D <= ((iobs/TS_FSM_FFd1 AND IOU0) OR (NOT nUDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1) OR (iobs/IOU1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1)); |
| MCKE <= '1'; |
|
FDCPE_QoSEN: FDCPE port map (QoSEN,QoSEN_D,FCLK,'0','0',QoSEN_CE);
QoSEN_D <= (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3)); QoSEN_CE <= (nAS_FSB AND NOT fsb/ASrf); |
|
RA(0) <= ((ram/RASEL AND A_FSB(1))
OR (NOT ram/RASEL AND A_FSB(9))); |
|
RA(1) <= ((A_FSB(10) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(2))); |
|
RA(2) <= ((A_FSB(16) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7))); |
|
RA(3) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL)); |
|
RA(4) <= ((A_FSB(11) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(3))); |
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RA(5) <= ((A_FSB(12) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(4))); |
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RA(6) <= ((A_FSB(13) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(5))); |
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RA(7) <= ((A_FSB(14) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(6))); |
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RA(8) <= ((A_FSB(21) AND ram/RASEL)
OR (A_FSB(18) AND NOT ram/RASEL)); |
|
RA(9) <= ((A_FSB(15) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(8))); |
|
RA(10) <= ((A_FSB(17) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7))); |
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RA(11) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL)); |
|
FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
RAMReady_D <= ((NOT RefUrg AND NOT RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND BACTr) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND fsb/ASrf) OR (nAS_FSB AND NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT fsb/ASrf) OR (NOT RefUrg AND ram/RS(1) AND ram/RS(0)) OR (ram/RefDone AND ram/RS(1) AND ram/RS(0)) OR (ram/RS(1) AND ram/RS(0) AND ram/RS(2)) OR (nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2)) OR (ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))); |
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FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
RefReq_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3)); RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1)); |
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FDCPE_RefUrg: FDCPE port map (RefUrg,RefUrg_D,FCLK,'0','0',RefUrg_CE);
RefUrg_D <= (NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3)); RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1)); |
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FDCPE_RnW_IOB: FDCPE port map (RnW_IOB_I,RnW_IOB,NOT C16M,'0','0');
RnW_IOB <= ((IORW) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd2) OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd2) OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd2)); RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z'; RnW_IOB_OE <= NOT nAoutOE; |
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FDCPE_SndQoSReady: FDCPE port map (SndQoSReady,SndQoSReady_D,FCLK,'0','0');
SndQoSReady_D <= ((cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND cnt/Wait(3) AND fsb/ASrf) OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND cnt/Wait(3)) OR (NOT nAS_FSB AND SndQoSReady) OR (NOT nAS_FSB AND cnt/QoSCSr) OR (SndQoSReady AND fsb/ASrf) OR (cnt/QoSCSr AND fsb/ASrf) OR (nAS_FSB AND NOT cnt/SndQS(0) AND NOT cnt/SndQS(1) AND NOT fsb/ASrf)); |
| FDCPE_cnt/C8Mr0: FDCPE port map (cnt/C8Mr(0),C8M,FCLK,'0','0'); |
| FDCPE_cnt/C8Mr1: FDCPE port map (cnt/C8Mr(1),cnt/C8Mr(0),FCLK,'0','0'); |
| FDCPE_cnt/C8Mr2: FDCPE port map (cnt/C8Mr(2),cnt/C8Mr(1),FCLK,'0','0'); |
| FDCPE_cnt/C8Mr3: FDCPE port map (cnt/C8Mr(3),cnt/C8Mr(2),FCLK,'0','0'); |
| FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0'); |
| FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0'); |
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FTCPE_cnt/IS0: FTCPE port map (cnt/IS(0),cnt/IS_T(0),FCLK,'0','0');
cnt/IS_T(0) <= ((NOT cnt/nPOR AND cnt/IS(0)) OR (cnt/nPOR AND NOT cnt/IS(1) AND cnt/LTimerTick) OR (cnt/nPOR AND NOT cnt/IS(0) AND cnt/LTimerTick AND nIPL2)); |
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FDCPE_cnt/IS1: FDCPE port map (cnt/IS(1),cnt/IS_D(1),FCLK,'0','0');
cnt/IS_D(1) <= ((cnt/nPOR AND cnt/IS(1)) OR (cnt/nPOR AND cnt/IS(0) AND cnt/LTimerTick)); |
| FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/TimerTick); |
| FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/TimerTick); |
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FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1)); |
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FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2)); |
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FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3)); |
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FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4)); |
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FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5)); |
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FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6)); |
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FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7)); |
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FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8)); |
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FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9)); |
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FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/TimerTick);
cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9)); |
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FDCPE_cnt/LTimerTick: FDCPE port map (cnt/LTimerTick,cnt/LTimerTick_D,FCLK,'0','0');
cnt/LTimerTick_D <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND cnt/LTimer(11) AND cnt/TimerTick); |
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FDCPE_cnt/QS0: FDCPE port map (cnt/QS(0),cnt/QS_D(0),FCLK,'0','0');
cnt/QS_D(0) <= ((cnt/QS(0) AND cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr) OR (NOT cnt/QS(0) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr) OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr)); |
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FDCPE_cnt/QS1: FDCPE port map (cnt/QS(1),cnt/QS_D(1),FCLK,'0','0');
cnt/QS_D(1) <= ((cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr) OR (NOT cnt/QS(1) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr) OR (NOT cnt/QS(0) AND cnt/QS(1) AND cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr) OR (NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr)); |
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FTCPE_cnt/QS2: FTCPE port map (cnt/QS(2),cnt/QS_T(2),FCLK,'0','0');
cnt/QS_T(2) <= ((NOT cnt/QS(2) AND cnt/QoSCSr) OR (NOT cnt/QS(2) AND cnt/SndQoSCSr) OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND cnt/QS(3) AND cnt/TimerTick) OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND cnt/QS(2) AND cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr)); |
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FDCPE_cnt/QS3: FDCPE port map (cnt/QS(3),cnt/QS_D(3),FCLK,'0','0');
cnt/QS_D(3) <= ((NOT cnt/QS(3) AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr) OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND cnt/TimerTick AND NOT cnt/QoSCSr AND NOT cnt/SndQoSCSr)); |
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FDCPE_cnt/QoSCSr: FDCPE port map (cnt/QoSCSr,cnt/QoSCSr_D,FCLK,'0','0');
cnt/QoSCSr_D <= ((nAS_FSB AND nRES.PIN AND NOT fsb/ASrf) OR (A_FSB(21) AND NOT A_FSB(23) AND nRES.PIN) OR (NOT A_FSB(21) AND NOT A_FSB(20) AND nRES.PIN) OR (NOT A_FSB(20) AND NOT A_FSB(22) AND nRES.PIN) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND nRES.PIN)); |
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FDCPE_cnt/SndQS0: FDCPE port map (cnt/SndQS(0),cnt/SndQS_D(0),FCLK,'0','0');
cnt/SndQS_D(0) <= ((cnt/SndQoSCSr) OR (cnt/SndQS(0) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr) OR (NOT cnt/SndQS(0) AND cnt/SndQS(1) AND cnt/TimerTick AND NOT cnt/QoSCSr)); |
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FDCPE_cnt/SndQS1: FDCPE port map (cnt/SndQS(1),cnt/SndQS_D(1),FCLK,'0','0');
cnt/SndQS_D(1) <= ((cnt/SndQoSCSr) OR (cnt/SndQS(0) AND cnt/SndQS(1) AND NOT cnt/QoSCSr) OR (cnt/SndQS(1) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr)); |
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FDCPE_cnt/SndQoSCSr: FDCPE port map (cnt/SndQoSCSr,cnt/SndQoSCSr_D,FCLK,'0','0');
cnt/SndQoSCSr_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nAS_FSB AND NOT nWE_FSB AND A_FSB(8)) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nAS_FSB AND NOT nWE_FSB AND A_FSB(9)) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nAS_FSB AND NOT nWE_FSB AND A_FSB(8)) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nAS_FSB AND NOT nWE_FSB AND A_FSB(9))); |
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FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1)); cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1)); |
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FTCPE_cnt/Timer1: FTCPE port map (cnt/Timer(1),cnt/Timer_T(1),FCLK,'0','0',cnt/Timer_CE(1));
cnt/Timer_T(1) <= ((cnt/Timer(0)) OR (cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1))); cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1)); |
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FTCPE_cnt/Timer2: FTCPE port map (cnt/Timer(2),cnt/Timer_T(2),FCLK,'0','0',cnt/Timer_CE(2));
cnt/Timer_T(2) <= (cnt/Timer(0) AND cnt/Timer(1)); cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1)); |
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FTCPE_cnt/Timer3: FTCPE port map (cnt/Timer(3),cnt/Timer_T(3),FCLK,'0','0',cnt/Timer_CE(3));
cnt/Timer_T(3) <= ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2)) OR (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1))); cnt/Timer_CE(3) <= (NOT cnt/Er(0) AND cnt/Er(1)); |
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FDCPE_cnt/TimerTick: FDCPE port map (cnt/TimerTick,cnt/TimerTick_D,FCLK,'0','0');
cnt/TimerTick_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1)); |
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FTCPE_cnt/Wait0: FTCPE port map (cnt/Wait(0),cnt/Wait_T(0),FCLK,'0','0');
cnt/Wait_T(0) <= (nAS_FSB AND NOT cnt/Wait(0) AND NOT fsb/ASrf); |
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FDCPE_cnt/Wait1: FDCPE port map (cnt/Wait(1),cnt/Wait_D(1),FCLK,'0','0');
cnt/Wait_D(1) <= ((nAS_FSB AND NOT fsb/ASrf) OR (cnt/Wait(0) AND cnt/Wait(1)) OR (NOT cnt/Wait(0) AND NOT cnt/Wait(1))); |
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FTCPE_cnt/Wait2: FTCPE port map (cnt/Wait(2),cnt/Wait_T(2),FCLK,'0','0');
cnt/Wait_T(2) <= ((nAS_FSB AND cnt/Wait(2) AND NOT fsb/ASrf) OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1)) OR (cnt/Wait(0) AND cnt/Wait(1) AND fsb/ASrf)); |
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FTCPE_cnt/Wait3: FTCPE port map (cnt/Wait(3),cnt/Wait_T(3),FCLK,'0','0');
cnt/Wait_T(3) <= ((nAS_FSB AND cnt/Wait(3) AND NOT fsb/ASrf) OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2)) OR (cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND fsb/ASrf)); |
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FTCPE_cnt/nPOR: FTCPE port map (cnt/nPOR,cnt/nPOR_T,FCLK,'0','0');
cnt/nPOR_T <= ((NOT cnt/nPOR AND NOT cnt/C8Mr(1) AND cnt/C8Mr(0)) OR (cnt/nPOR AND cnt/C8Mr(1) AND cnt/C8Mr(2) AND cnt/C8Mr(0) AND cnt/C8Mr(3)) OR (cnt/nPOR AND NOT cnt/C8Mr(1) AND NOT cnt/C8Mr(2) AND NOT cnt/C8Mr(0) AND NOT cnt/C8Mr(3))); |
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FTCPE_cs/Overlay: FTCPE port map (cs/Overlay,cs/Overlay_T,FCLK,'0','0');
cs/Overlay_T <= ((nAS_FSB AND NOT nRES.PIN AND NOT cs/Overlay AND NOT fsb/ASrf) OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND cs/Overlay) OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND cs/Overlay AND fsb/ASrf)); |
| FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0'); |
| FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0'); |
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FDCPE_iobm/DoutOE: FDCPE port map (iobm/DoutOE,iobm/DoutOE_D,C16M,'0','0');
iobm/DoutOE_D <= ((iobm/IOS_FSM_FFd3 AND iobm/DoutOE) OR (iobm/IOS_FSM_FFd4 AND iobm/DoutOE) OR (iobm/IOS_FSM_FFd5 AND iobm/DoutOE) OR (iobm/IOS_FSM_FFd6 AND iobm/DoutOE) OR (NOT IORW AND iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOREQr)); |
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FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er) OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3) AND E) OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3) AND NOT iobm/Er)); |
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FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1)) OR (NOT iobm/ES(0) AND NOT iobm/ES(1)) OR (NOT E AND iobm/Er) OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3))); |
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FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E) OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er) OR (iobm/ES(2) AND NOT E AND iobm/Er)); |
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FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er) OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND E) OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND NOT iobm/Er) OR (iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND iobm/ES(3))); |
| FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0'); |
| FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,C16M,'0','0'); |
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FDCPE_iobm/IOS0: FDCPE port map (iobm/IOS0,iobm/IOS0_D,C16M,'0','0');
iobm/IOS0_D <= ((iobm/IOS_FSM_FFd1) OR (iobm/IOS_FSM_FFd7 AND iobm/C8Mr) OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr) OR (iobm/IOS_FSM_FFd7 AND nAoutOE) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd2 AND iobm/IOS0)); |
| FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0'); |
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FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
iobm/IOS_FSM_FFd2_D <= ((IOBERR AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr) OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)); |
|
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd4) OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr) OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3)); |
| FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0'); |
| FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0'); |
|
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
iobm/IOS_FSM_FFd6_D <= (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOREQr AND NOT nAoutOE); |
|
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1) OR (NOT iobm/C8Mr AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1 AND NOT nAoutOE)); |
| FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0'); |
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FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2); |
| FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0'); |
| FDCPE_iobs/IODONEr: FDCPE port map (iobs/IODONEr,IODONE,FCLK,'0','0'); |
| FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1); |
|
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
iobs/IORW1_T <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)); |
| FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1); |
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FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
iobs/Load1_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)); |
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FTCPE_iobs/Sent: FTCPE port map (iobs/Sent,iobs/Sent_T,FCLK,'0','0');
iobs/Sent_T <= ((A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1) OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1) OR (nAS_FSB AND iobs/Sent AND NOT fsb/ASrf) OR (A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (A_FSB(23) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1) OR (NOT nAS_FSB AND NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)); |
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FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)); |
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FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0');
iobs/TS_FSM_FFd2_D <= ((NOT A_FSB(17) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(21) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(20) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(19) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(18) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT QoSEN AND nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2) OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr) OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1) OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND nADoutLE1) OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)); |
| nADoutLE0 <= (NOT ALE0M AND NOT ALE0S); |
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FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
nADoutLE1_D <= ((iobs/Load1) OR (NOT iobs/Clear1 AND NOT nADoutLE1)); |
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FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)); nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z'; nAS_IOB_OE <= NOT nAoutOE; |
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FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
nAoutOE_D <= (NOT nBR_IOB AND cnt/IS(1) AND cnt/IS(0)); |
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FDCPE_nBERR_FSB: FDCPE port map (nBERR_FSB,nBERR_FSB_D,FCLK,'0','0');
nBERR_FSB_D <= ((nAS_FSB AND NOT fsb/ASrf) OR (NOT iobs/Sent AND nBERR_FSB) OR (NOT IOBERR AND nBERR_FSB)); |
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FDCPE_nBR_IOB: FDCPE port map (nBR_IOB,nBR_IOB_D,FCLK,'0','0');
nBR_IOB_D <= ((nBR_IOB AND cnt/IS(1)) OR (cnt/IS(1) AND NOT cnt/IS(0) AND NOT nIPL2)); |
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FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,ram/RefCAS,nCAS_PRE);
nCAS_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2)) OR (NOT ram/RS(1) AND NOT ram/RS(0) AND ram/RS(2))); nCAS_PRE <= (nAS_FSB AND ram/CASEndEN); |
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FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0',nAS_FSB);
nDTACK_FSB_D <= ((A_FSB(21) AND A_FSB(22) AND NOT IONPReady) OR (A_FSB(20) AND A_FSB(22) AND NOT IONPReady) OR (A_FSB(20) AND A_FSB(22) AND NOT SndQoSReady) OR (NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady) OR (A_FSB(21) AND A_FSB(22) AND NOT SndQoSReady) OR (NOT A_FSB(22) AND NOT SndQoSReady AND NOT RAMReady) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23)) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT IONPReady AND NOT nWE_FSB AND NOT nADoutLE1) OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT SndQoSReady AND NOT nWE_FSB AND NOT nADoutLE1) OR (A_FSB(23) AND NOT IONPReady) OR (A_FSB(23) AND NOT SndQoSReady) OR (QoSEN AND NOT IONPReady) OR (QoSEN AND NOT SndQoSReady)); |
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FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4); |
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nDinOE <= NOT (((A_FSB(23) AND NOT nAS_FSB AND nWE_FSB AND BACTr)
OR (A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND nWE_FSB AND BACTr) OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND nWE_FSB AND BACTr))); |
|
nDoutOE <= NOT (((iobm/DoutOE AND NOT nAoutOE)
OR (NOT iobm/IOREQr AND iobm/IOS0 AND NOT nAoutOE))); |
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FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
nLDS_IOB <= ((NOT IOL0) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)); nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z'; nLDS_IOB_OE <= NOT nAoutOE; |
| nOE <= '0'; |
| nRAMLWE <= NOT ((NOT nLDS_FSB AND NOT nWE_FSB AND ram/RASEL)); |
| nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL)); |
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nRAS <= NOT (((ram/RASrf)
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND RAMReady))); |
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nRES_I <= '0';
nRES <= nRES_I when nRES_OE = '1' else 'Z'; nRES_OE <= NOT nRESout; |
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FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
nRESout_D <= ((cnt/IS(1) AND cnt/IS(0) AND cnt/LTimerTick) OR (cnt/IS(1) AND cnt/IS(0) AND nRESout)); |
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nROMOE <= NOT (((NOT nAS_FSB AND cs/Overlay AND nWE_FSB)
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND nWE_FSB))); |
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nROMWE <= NOT ((NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
NOT nAS_FSB AND NOT nWE_FSB)); |
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FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
nUDS_IOB <= ((NOT IOU0) OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6) OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)); nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z'; nUDS_IOB_OE <= NOT nAoutOE; |
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FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C8M,'0','0');
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3)) OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(2) AND NOT iobm/ES(1) AND NOT iobm/ES(3) AND IOACT AND iobm/VPAr)); nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z'; nVMA_IOB_OE <= NOT nAoutOE; |
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FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
nVPA_FSB_D <= (A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23) AND IONPReady AND SndQoSReady); |
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FDCPE_ram/CASEndEN: FDCPE port map (ram/CASEndEN,ram/CASEndEN_D,NOT FCLK,'0','0');
ram/CASEndEN_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))); |
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FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
ram/RASEL_D <= ((NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2)) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT cs/Overlay AND NOT ram/RS(1) AND NOT ram/RS(2)) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT ram/RS(1) AND NOT ram/RS(2) AND fsb/ASrf)); |
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FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RASrf_D,NOT FCLK,'0','0');
ram/RASrf_D <= ((NOT ram/RS(1) AND ram/RS(0)) OR (NOT ram/RS(1) AND ram/RS(2))); |
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FDCPE_ram/RS0: FDCPE port map (ram/RS(0),ram/RS_D(0),FCLK,'0','0');
ram/RS_D(0) <= ((nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2) AND fsb/ASrf) OR (ram/RS(1) AND NOT ram/RS(0)) OR (NOT ram/RS(0) AND ram/RS(2)) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT nAS_FSB AND NOT ram/RS(0) AND RAMReady) OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT ram/RS(0) AND RAMReady AND fsb/ASrf) OR (NOT nAS_FSB AND nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))); |
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FTCPE_ram/RS1: FTCPE port map (ram/RS(1),ram/RS_T(1),FCLK,'0','0');
ram/RS_T(1) <= ((NOT ram/RS(0)) OR (NOT nAS_FSB AND nDTACK_FSB AND NOT ram/RS(1) AND NOT ram/RS(2)) OR (nDTACK_FSB AND NOT ram/RS(1) AND NOT ram/RS(2) AND fsb/ASrf)); |
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FTCPE_ram/RS2: FTCPE port map (ram/RS(2),ram/RS_T(2),FCLK,'0','0');
ram/RS_T(2) <= ((ram/RS(1) AND ram/RS(0) AND ram/RS(2)) OR (RefUrg AND NOT ram/RefDone AND ram/RS(1) AND ram/RS(0)) OR (A_FSB(22) AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr AND fsb/ASrf) OR (A_FSB(23) AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr AND fsb/ASrf) OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (nAS_FSB AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT fsb/ASrf) OR (A_FSB(22) AND NOT nAS_FSB AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr) OR (A_FSB(23) AND NOT nAS_FSB AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr)); |
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FDCPE_ram/RefCAS: FDCPE port map (ram/RefCAS,ram/RefCAS_D,FCLK,'0','0');
ram/RefCAS_D <= ((A_FSB(22) AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr AND fsb/ASrf) OR (A_FSB(23) AND NOT nAS_FSB AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr) OR (A_FSB(23) AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr AND fsb/ASrf) OR (RefUrg AND NOT ram/RefDone AND ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2)) OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)) OR (nAS_FSB AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT fsb/ASrf) OR (A_FSB(22) AND NOT nAS_FSB AND NOT ram/RefDone AND RefReq AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr)); |
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FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
ram/RefDone_D <= ((ram/RefDone AND RefReq) OR (RefReq AND ram/RS(2))); |
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Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |