Timing Report

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Design Name WarpSE
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sat Mar 25 00:05:47 2023
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for E
Clock to Setup (tCYC) 11.400 ns.
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 7.900 ns.
Clock Pad to Output Pad Delay (tCO) 14.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_CLK_IOB 142.8 10.0 136 0
TS_CLK_FSB 40.0 11.4 164 0
TS_CLK2X_IOB 66.6 11.0 100 0


Constraint: TS_CLK_IOB

Description: PERIOD:CLK_IOB:142.857nS:HIGH:71.428nS
Path Requirement (ns) Delay (ns) Slack (ns)
cnt/IPL2r.Q to cnt/PORS_FSM_FFd1.D 142.800 10.000 132.800
cnt/IPL2r.Q to nBR_IOB.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<0>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<1>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<2>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<3>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<4>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<0>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<10>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<10>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<10>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<10>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<11>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<11>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<11>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<12>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<12>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<0>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<1>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<2>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<3>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<4>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/PORS_FSM_FFd1.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/PORS_FSM_FFd2.D 142.800 10.000 132.800
cnt/LTimer<13>.Q to cnt/nRESout.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<1>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<2>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<3>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<4>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<1>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<2>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<3>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<4>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<2>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<3>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<4>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<3>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<4>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<4>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<5>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<5>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<6>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<6>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<7>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<7>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<8>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<8>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<8>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<8>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<8>.Q to cnt/LTimer<8>.D 142.800 10.000 132.800
cnt/LTimer<8>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/LTimer<9>.Q to cnt/LTimer<10>.D 142.800 10.000 132.800
cnt/LTimer<9>.Q to cnt/LTimer<11>.D 142.800 10.000 132.800
cnt/LTimer<9>.Q to cnt/LTimer<12>.D 142.800 10.000 132.800
cnt/LTimer<9>.Q to cnt/LTimer<13>.D 142.800 10.000 132.800
cnt/LTimer<9>.Q to cnt/LTimer<9>.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd1.Q to cnt/PORS_FSM_FFd1.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd1.Q to cnt/PORS_FSM_FFd2.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd1.Q to cnt/nRESout.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd1.Q to nAoutOE.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd1.Q to nBR_IOB.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd2.Q to cnt/PORS_FSM_FFd1.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd2.Q to cnt/PORS_FSM_FFd2.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd2.Q to cnt/nRESout.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd2.Q to nAoutOE.D 142.800 10.000 132.800
cnt/PORS_FSM_FFd2.Q to nBR_IOB.D 142.800 10.000 132.800
cnt/nRESout.Q to cnt/nRESout.D 142.800 10.000 132.800
nBR_IOB.Q to nAoutOE.D 142.800 10.000 132.800
nBR_IOB.Q to nBR_IOB.D 142.800 10.000 132.800


Constraint: TS_CLK_FSB

Description: PERIOD:CLK_FSB:40.000nS:HIGH:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
cs/nOverlay1.Q to fsb/VPA.D 40.000 11.400 28.600
cs/nOverlay1.Q to iobs/IORW0.D 40.000 11.400 28.600
cs/nOverlay1.Q to iobs/Once.D 40.000 11.400 28.600
cs/nOverlay1.Q to ram/RAMReady.D 40.000 11.400 28.600
cs/nOverlay1.Q to ram/RASEL.D 40.000 11.400 28.600
fsb/ASrf.Q to fsb/VPA.D 20.000 11.400 8.600
fsb/ASrf.Q to iobs/IORW0.D 20.000 11.400 8.600
fsb/ASrf.Q to nDTACK_FSB.D 20.000 11.400 8.600
fsb/ASrf.Q to ram/RASEL.D 20.000 11.400 8.600
fsb/Ready1r.Q to fsb/VPA.D 40.000 11.400 28.600
fsb/Ready1r.Q to nDTACK_FSB.D 40.000 11.400 28.600
fsb/VPA.Q to fsb/VPA.D 40.000 11.400 28.600
iobs/IORW0.Q to iobs/IORW0.D 40.000 11.400 28.600
iobs/IOReady.Q to fsb/VPA.D 40.000 11.400 28.600
iobs/IOReady.Q to nDTACK_FSB.D 40.000 11.400 28.600
iobs/Once.Q to iobs/IORW0.D 40.000 11.400 28.600
iobs/Once.Q to iobs/Once.D 40.000 11.400 28.600
iobs/PS_FSM_FFd1.Q to iobs/IORW0.D 40.000 11.400 28.600
iobs/PS_FSM_FFd2.Q to iobs/IOREQ.D 40.000 11.400 28.600
iobs/PS_FSM_FFd2.Q to iobs/IORW0.D 40.000 11.400 28.600
nADoutLE1.Q to fsb/VPA.D 40.000 11.400 28.600
nADoutLE1.Q to iobs/IOREQ.D 40.000 11.400 28.600
nADoutLE1.Q to iobs/IORW0.D 40.000 11.400 28.600
nDTACK_FSB.Q to nDTACK_FSB.D 40.000 11.400 28.600
ram/RAMEN.Q to ram/RAMReady.D 40.000 11.400 28.600
ram/RAMEN.Q to ram/RASEL.D 40.000 11.400 28.600
ram/RS_FSM_FFd2.Q to ram/RAMReady.D 40.000 11.400 28.600
ram/RS_FSM_FFd2.Q to ram/RASEL.D 40.000 11.400 28.600
ram/RS_FSM_FFd3.Q to ram/RAMReady.D 40.000 11.400 28.600
ram/RS_FSM_FFd3.Q to ram/RASEL.D 40.000 11.400 28.600
ram/RefReq.Q to ram/RAMReady.D 40.000 11.400 28.600
ram/RefUrgent.Q to ram/RAMReady.D 40.000 11.400 28.600
cs/nOverlay1.Q to fsb/Ready1r.D 40.000 11.000 29.000
cs/nOverlay1.Q to iobs/IOREQ.D 40.000 11.000 29.000
cs/nOverlay1.Q to iobs/IORW1.D 40.000 11.000 29.000
cs/nOverlay1.Q to iobs/Load1.D 40.000 11.000 29.000
cs/nOverlay1.Q to iobs/PS_FSM_FFd2.D 40.000 11.000 29.000
cs/nOverlay1.Q to nDTACK_FSB.D 40.000 11.000 29.000
cs/nOverlay1.Q to ram/RAMEN.D 40.000 11.000 29.000
cs/nOverlay1.Q to ram/RS_FSM_FFd1.D 40.000 11.000 29.000
cs/nOverlay1.Q to ram/RS_FSM_FFd2.D 40.000 11.000 29.000
fsb/ASrf.Q to fsb/Ready0r.D 20.000 11.000 9.000
fsb/ASrf.Q to iobs/IORW1.D 20.000 11.000 9.000
fsb/ASrf.Q to iobs/IOReady.D 20.000 11.000 9.000
fsb/ASrf.Q to ram/RAMEN.D 20.000 11.000 9.000
fsb/ASrf.Q to ram/RS_FSM_FFd1.D 20.000 11.000 9.000
fsb/ASrf.Q to ram/RS_FSM_FFd2.D 20.000 11.000 9.000
fsb/ASrf.Q to ram/RS_FSM_FFd3.D 20.000 11.000 9.000
fsb/Ready0r.Q to fsb/VPA.D 40.000 11.000 29.000
fsb/Ready0r.Q to nDTACK_FSB.D 40.000 11.000 29.000
fsb/Ready1r.Q to fsb/Ready1r.D 40.000 11.000 29.000
iobs/IOACTr.Q to iobs/IOReady.D 40.000 11.000 29.000
iobs/IORW1.Q to iobs/IORW1.D 40.000 11.000 29.000
iobs/IOReady.Q to fsb/Ready1r.D 40.000 11.000 29.000
iobs/IOReady.Q to iobs/IOReady.D 40.000 11.000 29.000
iobs/Once.Q to iobs/IOReady.D 40.000 11.000 29.000
iobs/PS_FSM_FFd1.Q to iobs/IORW1.D 40.000 11.000 29.000
iobs/PS_FSM_FFd1.Q to iobs/Once.D 40.000 11.000 29.000
iobs/PS_FSM_FFd1.Q to iobs/PS_FSM_FFd2.D 40.000 11.000 29.000
iobs/PS_FSM_FFd2.Q to iobs/IORW1.D 40.000 11.000 29.000
iobs/PS_FSM_FFd2.Q to iobs/IOReady.D 40.000 11.000 29.000
iobs/PS_FSM_FFd2.Q to iobs/Once.D 40.000 11.000 29.000
iobs/PS_FSM_FFd2.Q to iobs/PS_FSM_FFd2.D 40.000 11.000 29.000
nADoutLE1.Q to fsb/Ready1r.D 40.000 11.000 29.000
nADoutLE1.Q to iobs/IOReady.D 40.000 11.000 29.000
nADoutLE1.Q to iobs/Once.D 40.000 11.000 29.000
nADoutLE1.Q to iobs/PS_FSM_FFd2.D 40.000 11.000 29.000
ram/BACTr.Q to ram/RAMReady.D 40.000 11.000 29.000
ram/BACTr.Q to ram/RASEL.D 40.000 11.000 29.000
ram/RAMEN.Q to ram/RAMEN.D 40.000 11.000 29.000
ram/RAMEN.Q to ram/RS_FSM_FFd1.D 40.000 11.000 29.000
ram/RAMReady.Q to fsb/VPA.D 40.000 11.000 29.000
ram/RAMReady.Q to nDTACK_FSB.D 40.000 11.000 29.000
ram/RS_FSM_FFd1.Q to ram/RAMEN.D 40.000 11.000 29.000
ram/RS_FSM_FFd1.Q to ram/RS_FSM_FFd1.D 40.000 11.000 29.000
ram/RS_FSM_FFd1.Q to ram/RS_FSM_FFd3.D 40.000 11.000 29.000
ram/RS_FSM_FFd2.Q to ram/RS_FSM_FFd1.D 40.000 11.000 29.000
ram/RS_FSM_FFd2.Q to ram/RS_FSM_FFd2.D 40.000 11.000 29.000
ram/RS_FSM_FFd2.Q to ram/RS_FSM_FFd3.D 40.000 11.000 29.000
ram/RS_FSM_FFd3.Q to ram/RS_FSM_FFd2.D 40.000 11.000 29.000
ram/RS_FSM_FFd3.Q to ram/RS_FSM_FFd3.D 40.000 11.000 29.000
ram/RefReq.Q to ram/RASEL.D 40.000 11.000 29.000
ram/RefUrgent.Q to ram/RASEL.D 40.000 11.000 29.000
ram/RefUrgent.Q to ram/RS_FSM_FFd1.D 40.000 11.000 29.000
ram/RefUrgent.Q to ram/RS_FSM_FFd2.D 40.000 11.000 29.000
ram/RefUrgent.Q to ram/RS_FSM_FFd3.D 40.000 11.000 29.000
cs/nOverlay0.Q to cs/nOverlay0.D 40.000 10.000 30.000
cs/nOverlay0.Q to cs/nOverlay1.D 40.000 10.000 30.000
cs/nOverlay1.Q to fsb/Ready0r.D 40.000 10.000 30.000
cs/nOverlay1.Q to ram/RS_FSM_FFd3.D 40.000 10.000 30.000
fsb/ASrf.Q to cs/nOverlay0.D 20.000 10.000 10.000
fsb/ASrf.Q to cs/nOverlay1.CE 40.000 10.000 30.000
fsb/ASrf.Q to fsb/Ready1r.D 20.000 10.000 10.000
fsb/ASrf.Q to iobs/IOREQ.D 20.000 10.000 10.000
fsb/ASrf.Q to iobs/Load1.D 20.000 10.000 10.000
fsb/ASrf.Q to iobs/Once.D 20.000 10.000 10.000
fsb/ASrf.Q to iobs/PS_FSM_FFd2.D 20.000 10.000 10.000
fsb/ASrf.Q to nBERR_FSB.D 20.000 10.000 10.000
fsb/ASrf.Q to ram/BACTr.D 20.000 10.000 10.000
fsb/ASrf.Q to ram/RAMReady.D 20.000 10.000 10.000
fsb/Ready0r.Q to fsb/Ready0r.D 40.000 10.000 30.000
iobs/Clear1.Q to nADoutLE1.D 40.000 10.000 30.000
iobs/IOACTr.Q to iobs/IOREQ.D 40.000 10.000 30.000
iobs/IOACTr.Q to iobs/PS_FSM_FFd1.D 40.000 10.000 30.000
iobs/IOACTr.Q to iobs/PS_FSM_FFd2.D 40.000 10.000 30.000
iobs/IOACTr.Q to nBERR_FSB.D 40.000 10.000 30.000
iobs/IOL1.Q to iobs/IOL0.D 40.000 10.000 30.000
iobs/IORW1.Q to iobs/IORW0.D 40.000 10.000 30.000
iobs/IOU1.Q to iobs/IOU0.D 40.000 10.000 30.000
iobs/Load1.Q to iobs/IOL1.CE 40.000 10.000 30.000
iobs/Load1.Q to iobs/IOU1.CE 40.000 10.000 30.000
iobs/Load1.Q to nADoutLE1.D 40.000 10.000 30.000
iobs/Once.Q to iobs/IOREQ.D 40.000 10.000 30.000
iobs/Once.Q to iobs/IORW1.D 40.000 10.000 30.000
iobs/Once.Q to iobs/Load1.D 40.000 10.000 30.000
iobs/Once.Q to iobs/PS_FSM_FFd2.D 40.000 10.000 30.000
iobs/Once.Q to nBERR_FSB.D 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/ALE0.D 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/Clear1.D 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/IOL0.CE 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/IOREQ.D 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/IOU0.CE 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/Load1.D 40.000 10.000 30.000
iobs/PS_FSM_FFd1.Q to iobs/PS_FSM_FFd1.D 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to iobs/ALE0.D 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to iobs/Clear1.D 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to iobs/IOL0.CE 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to iobs/IOU0.CE 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to iobs/Load1.D 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to iobs/PS_FSM_FFd1.D 40.000 10.000 30.000
iobs/PS_FSM_FFd2.Q to nBERR_FSB.D 40.000 10.000 30.000
nADoutLE1.Q to iobs/Clear1.D 40.000 10.000 30.000
nADoutLE1.Q to iobs/IOL0.D 40.000 10.000 30.000
nADoutLE1.Q to iobs/IORW1.D 40.000 10.000 30.000
nADoutLE1.Q to iobs/IOU0.D 40.000 10.000 30.000
nADoutLE1.Q to iobs/Load1.D 40.000 10.000 30.000
nADoutLE1.Q to nADoutLE1.D 40.000 10.000 30.000
nADoutLE1.Q to nBERR_FSB.D 40.000 10.000 30.000
nADoutLE1.Q to nDTACK_FSB.D 40.000 10.000 30.000
nBERR_FSB.Q to nBERR_FSB.D 40.000 10.000 30.000
ram/BACTr.Q to ram/RAMEN.D 40.000 10.000 30.000
ram/BACTr.Q to ram/RS_FSM_FFd2.D 40.000 10.000 30.000
ram/RAMEN.Q to ram/RS_FSM_FFd3.D 40.000 10.000 30.000
ram/RAMReady.Q to fsb/Ready0r.D 40.000 10.000 30.000
ram/RASEL.Q to nCAS.D 20.000 10.000 10.000
ram/RS_FSM_FFd1.Q to ram/RAMReady.D 40.000 10.000 30.000
ram/RS_FSM_FFd1.Q to ram/RASEL.D 40.000 10.000 30.000
ram/RS_FSM_FFd1.Q to ram/RS_FSM_FFd2.D 40.000 10.000 30.000
ram/RS_FSM_FFd1.Q to ram/RefDone.D 40.000 10.000 30.000
ram/RS_FSM_FFd1.Q to ram/RefRAS.D 40.000 10.000 30.000
ram/RS_FSM_FFd2.Q to ram/RAMEN.D 40.000 10.000 30.000
ram/RS_FSM_FFd2.Q to ram/RefDone.D 40.000 10.000 30.000
ram/RS_FSM_FFd2.Q to ram/RefRAS.D 40.000 10.000 30.000
ram/RS_FSM_FFd3.Q to ram/RAMEN.D 40.000 10.000 30.000
ram/RS_FSM_FFd3.Q to ram/RS_FSM_FFd1.D 40.000 10.000 30.000
ram/RefDone.Q to ram/RefDone.D 40.000 10.000 30.000
ram/RefDone.Q to ram/RefReq.D 40.000 10.000 30.000
ram/RefDone.Q to ram/RefUrgent.D 40.000 10.000 30.000
ram/RefReq.Q to ram/RAMEN.D 40.000 10.000 30.000
ram/RefReq.Q to ram/RS_FSM_FFd2.D 40.000 10.000 30.000
ram/RefReqSync.Q to ram/RefDone.D 40.000 10.000 30.000
ram/RefReqSync.Q to ram/RefReq.D 40.000 10.000 30.000
ram/RefUrgent.Q to ram/RAMEN.D 40.000 10.000 30.000
ram/RegUrgentSync.Q to ram/RefUrgent.D 40.000 10.000 30.000


Constraint: TS_CLK2X_IOB

Description: PERIOD:CLK2X_IOB:66.666nS:HIGH:33.333nS
Path Requirement (ns) Delay (ns) Slack (ns)
iobm/BERRrf.Q to iobm/IOBERR.D 33.300 11.000 22.300
iobm/BERRrr.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/DTACKrf.Q to iobm/IOBERR.D 33.300 11.000 22.300
iobm/DTACKrr.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/IOBERR.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/IOS_FSM_FFd1.Q to iobm/IOACT.D 66.600 11.000 55.600
iobm/IOS_FSM_FFd1.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/IOS_FSM_FFd2.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/IOS_FSM_FFd3.Q to iobm/IOACT.D 66.600 11.000 55.600
iobm/IOS_FSM_FFd3.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/RESrf.Q to iobm/IOACT.D 33.300 11.000 22.300
iobm/RESrf.Q to iobm/IOBERR.D 33.300 11.000 22.300
iobm/RESrr.Q to iobm/IOACT.D 66.600 11.000 55.600
iobm/RESrr.Q to iobm/IOBERR.D 66.600 11.000 55.600
iobm/BERRrf.Q to iobm/IOACT.D 33.300 10.000 23.300
iobm/BERRrf.Q to iobm/IOS_FSM_FFd2.D 33.300 10.000 23.300
iobm/BERRrr.Q to iobm/IOACT.D 66.600 10.000 56.600
iobm/BERRrr.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/BG.Q to iobm/IOS_FSM_FFd3.D 66.600 10.000 56.600
iobm/DTACKrf.Q to iobm/IOACT.D 33.300 10.000 23.300
iobm/DTACKrf.Q to iobm/IOS_FSM_FFd2.D 33.300 10.000 23.300
iobm/DTACKrr.Q to iobm/IOACT.D 66.600 10.000 56.600
iobm/DTACKrr.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/ES<0>.Q to iobm/ES<0>.D 66.600 10.000 56.600
iobm/ES<0>.Q to iobm/ES<1>.D 66.600 10.000 56.600
iobm/ES<0>.Q to iobm/ES<2>.D 66.600 10.000 56.600
iobm/ES<0>.Q to iobm/ES<3>.D 66.600 10.000 56.600
iobm/ES<0>.Q to iobm/ES<4>.D 66.600 10.000 56.600
iobm/ES<0>.Q to iobm/ETACK.D 66.600 10.000 56.600
iobm/ES<0>.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/ES<1>.Q to iobm/ES<0>.D 66.600 10.000 56.600
iobm/ES<1>.Q to iobm/ES<1>.D 66.600 10.000 56.600
iobm/ES<1>.Q to iobm/ES<2>.D 66.600 10.000 56.600
iobm/ES<1>.Q to iobm/ES<3>.D 66.600 10.000 56.600
iobm/ES<1>.Q to iobm/ES<4>.D 66.600 10.000 56.600
iobm/ES<1>.Q to iobm/ETACK.D 66.600 10.000 56.600
iobm/ES<1>.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/ES<2>.Q to iobm/ES<0>.D 66.600 10.000 56.600
iobm/ES<2>.Q to iobm/ES<2>.D 66.600 10.000 56.600
iobm/ES<2>.Q to iobm/ES<3>.D 66.600 10.000 56.600
iobm/ES<2>.Q to iobm/ES<4>.D 66.600 10.000 56.600
iobm/ES<2>.Q to iobm/ETACK.D 66.600 10.000 56.600
iobm/ES<2>.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/ES<3>.Q to iobm/ES<0>.D 66.600 10.000 56.600
iobm/ES<3>.Q to iobm/ES<2>.D 66.600 10.000 56.600
iobm/ES<3>.Q to iobm/ES<3>.D 66.600 10.000 56.600
iobm/ES<3>.Q to iobm/ES<4>.D 66.600 10.000 56.600
iobm/ES<3>.Q to iobm/ETACK.D 66.600 10.000 56.600
iobm/ES<3>.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/ES<4>.Q to iobm/ES<0>.D 66.600 10.000 56.600
iobm/ES<4>.Q to iobm/ES<2>.D 66.600 10.000 56.600
iobm/ES<4>.Q to iobm/ES<4>.D 66.600 10.000 56.600
iobm/ES<4>.Q to iobm/ETACK.D 66.600 10.000 56.600
iobm/ES<4>.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/ETACK.Q to iobm/IOACT.D 66.600 10.000 56.600
iobm/ETACK.Q to iobm/IOBERR.D 66.600 10.000 56.600
iobm/ETACK.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/Er2.Q to iobm/ES<0>.D 66.600 10.000 56.600
iobm/Er2.Q to iobm/ES<1>.D 66.600 10.000 56.600
iobm/Er2.Q to iobm/ES<2>.D 66.600 10.000 56.600
iobm/Er2.Q to iobm/ES<3>.D 66.600 10.000 56.600
iobm/Er2.Q to iobm/ES<4>.D 66.600 10.000 56.600
iobm/IOACT.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/IOREQr.Q to iobm/ALE0.D 33.300 10.000 23.300
iobm/IOREQr.Q to iobm/IOACT.D 33.300 10.000 23.300
iobm/IOREQr.Q to iobm/IOS_FSM_FFd3.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd1.Q to iobm/ALE0.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd1.Q to iobm/IOS_FSM_FFd1.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd1.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd1.Q to iobm/IOS_FSM_FFd3.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd1.Q to nAS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd1.Q to nDinLE.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd1.Q to nLDS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd1.Q to nUDS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd2.Q to iobm/ALE0.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd2.Q to iobm/DoutOE.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd2.Q to iobm/IOACT.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd2.Q to iobm/IOS_FSM_FFd1.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd2.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd2.Q to iobm/IOS_FSM_FFd3.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd2.Q to nAS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd2.Q to nDinLE.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd2.Q to nLDS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd2.Q to nUDS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd3.Q to iobm/ALE0.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd3.Q to iobm/DoutOE.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd3.Q to iobm/IOS_FSM_FFd1.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd3.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd3.Q to iobm/IOS_FSM_FFd3.D 66.600 10.000 56.600
iobm/IOS_FSM_FFd3.Q to nAS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd3.Q to nLDS_IOB.D 33.300 10.000 23.300
iobm/IOS_FSM_FFd3.Q to nUDS_IOB.D 33.300 10.000 23.300
iobm/RESrf.Q to iobm/IOS_FSM_FFd2.D 33.300 10.000 23.300
iobm/RESrr.Q to iobm/IOS_FSM_FFd2.D 66.600 10.000 56.600
iobm/VPArf.Q to nVMA_IOB.D 33.300 10.000 23.300
iobm/VPArr.Q to nVMA_IOB.D 66.600 10.000 56.600
iobm/nASr.Q to iobm/BG.CE 66.600 10.000 56.600
nAS_IOB.Q to iobm/nASr.D 33.300 10.000 23.300
nVMA_IOB.Q to iobm/ETACK.D 66.600 10.000 56.600
nVMA_IOB.Q to nVMA_IOB.D 66.600 10.000 56.600



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
E 71.429 Limited by Clock Pulse Width for E
FCLK 87.719 Limited by Cycle Time for FCLK
C8M 100.000 Limited by Cycle Time for C8M
C16M 90.909 Limited by Cycle Time for C16M

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FCLK
Source Pad Setup to clk (edge) Hold to clk (edge)
A_FSB<10> 7.900 0.000
A_FSB<11> 7.900 0.000
A_FSB<12> 7.900 0.000
A_FSB<13> 7.900 0.000
A_FSB<14> 7.900 0.000
A_FSB<15> 7.900 0.000
A_FSB<16> 7.900 0.000
A_FSB<17> 7.900 0.000
A_FSB<18> 7.900 0.000
A_FSB<19> 7.900 0.000
A_FSB<20> 7.900 0.000
A_FSB<21> 7.900 0.000
A_FSB<22> 7.900 0.000
A_FSB<23> 7.900 0.000
A_FSB<8> 7.900 0.000
A_FSB<9> 7.900 0.000
nAS_FSB 7.900 0.000
nLDS_FSB 6.500 0.000
nUDS_FSB 6.500 0.000
nWE_FSB 7.900 0.000

Setup/Hold Times for Clock C8M
Source Pad Setup to clk (edge) Hold to clk (edge)
E 6.500 0.000
nIPL2 6.500 0.000

Setup/Hold Times for Clock C16M
Source Pad Setup to clk (edge) Hold to clk (edge)
C8M 7.500 0.000
nBERR_IOB 7.500 0.000
nBG_IOB 6.500 0.000
nDTACK_IOB 6.500 0.000
nRES 6.500 0.000
nVPA_IOB 6.500 0.000


Clock to Pad Timing

Clock FCLK to Pad
Destination Pad Clock (edge) to Pad
RA<4> 14.500
RA<5> 14.500
RA<6> 14.500
RA<8> 14.500
nRAMLWE 14.500
nROMCS 14.500
RA<0> 13.500
RA<1> 13.500
RA<2> 13.500
RA<3> 13.500
RA<7> 13.500
RA<9> 13.500
nADoutLE0 13.500
nRAMUWE 13.500
nRAS 13.500
nVPA_FSB 13.500
nADoutLE1 5.800
nBERR_FSB 5.800
nCAS 5.800
nDTACK_FSB 5.800

Clock C8M to Pad
Destination Pad Clock (edge) to Pad
nAS_IOB 14.500
nLDS_IOB 14.500
nRES 14.500
nUDS_IOB 14.500
nVMA_IOB 14.500
nDoutOE 13.500
nAoutOE 5.800
nBR_IOB 5.800

Clock C16M to Pad
Destination Pad Clock (edge) to Pad
nADoutLE0 13.500
nDoutOE 13.500
nAS_IOB 5.800
nDinLE 5.800
nLDS_IOB 5.800
nUDS_IOB 5.800
nVMA_IOB 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock E
Source Destination Delay
cnt/Timer<0>.Q cnt/RefReq.D 10.000
cnt/Timer<0>.Q cnt/RefUrgent.D 10.000
cnt/Timer<0>.Q cnt/Timer<0>.D 10.000
cnt/Timer<0>.Q cnt/Timer<1>.D 10.000
cnt/Timer<0>.Q cnt/Timer<2>.D 10.000
cnt/Timer<0>.Q cnt/Timer<3>.D 10.000
cnt/Timer<0>.Q cnt/TimerTC.D 10.000
cnt/Timer<1>.Q cnt/RefReq.D 10.000
cnt/Timer<1>.Q cnt/RefUrgent.D 10.000
cnt/Timer<1>.Q cnt/Timer<1>.D 10.000
cnt/Timer<1>.Q cnt/Timer<2>.D 10.000
cnt/Timer<1>.Q cnt/Timer<3>.D 10.000
cnt/Timer<1>.Q cnt/TimerTC.D 10.000
cnt/Timer<2>.Q cnt/RefReq.D 10.000
cnt/Timer<2>.Q cnt/RefUrgent.D 10.000
cnt/Timer<2>.Q cnt/Timer<2>.D 10.000
cnt/Timer<2>.Q cnt/Timer<3>.D 10.000
cnt/Timer<2>.Q cnt/TimerTC.D 10.000
cnt/Timer<3>.Q cnt/RefReq.D 10.000
cnt/Timer<3>.Q cnt/RefUrgent.D 10.000
cnt/Timer<3>.Q cnt/Timer<3>.D 10.000
cnt/Timer<3>.Q cnt/TimerTC.D 10.000
cnt/TimerTC.Q cnt/Timer<0>.D 10.000
cnt/TimerTC.Q cnt/Timer<1>.D 10.000
cnt/TimerTC.Q cnt/Timer<2>.D 10.000
cnt/TimerTC.Q cnt/Timer<3>.D 10.000

Clock to Setup for clock FCLK
Source Destination Delay
cs/nOverlay1.Q fsb/VPA.D 11.400
cs/nOverlay1.Q iobs/IORW0.D 11.400
cs/nOverlay1.Q iobs/Once.D 11.400
cs/nOverlay1.Q ram/RAMReady.D 11.400
cs/nOverlay1.Q ram/RASEL.D 11.400
fsb/ASrf.Q fsb/VPA.D 11.400
fsb/ASrf.Q iobs/IORW0.D 11.400
fsb/ASrf.Q nDTACK_FSB.D 11.400
fsb/ASrf.Q ram/RASEL.D 11.400
fsb/Ready1r.Q fsb/VPA.D 11.400
fsb/Ready1r.Q nDTACK_FSB.D 11.400
fsb/VPA.Q fsb/VPA.D 11.400
iobs/IORW0.Q iobs/IORW0.D 11.400
iobs/IOReady.Q fsb/VPA.D 11.400
iobs/IOReady.Q nDTACK_FSB.D 11.400
iobs/Once.Q iobs/IORW0.D 11.400
iobs/Once.Q iobs/Once.D 11.400
iobs/PS_FSM_FFd1.Q iobs/IORW0.D 11.400
iobs/PS_FSM_FFd2.Q iobs/IOREQ.D 11.400
iobs/PS_FSM_FFd2.Q iobs/IORW0.D 11.400
nADoutLE1.Q fsb/VPA.D 11.400
nADoutLE1.Q iobs/IOREQ.D 11.400
nADoutLE1.Q iobs/IORW0.D 11.400
nDTACK_FSB.Q nDTACK_FSB.D 11.400
ram/RAMEN.Q ram/RAMReady.D 11.400
ram/RAMEN.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd2.Q ram/RAMReady.D 11.400
ram/RS_FSM_FFd2.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd3.Q ram/RAMReady.D 11.400
ram/RS_FSM_FFd3.Q ram/RASEL.D 11.400
ram/RefReq.Q ram/RAMReady.D 11.400
ram/RefUrgent.Q ram/RAMReady.D 11.400
cs/nOverlay1.Q fsb/Ready1r.D 11.000
cs/nOverlay1.Q iobs/IOREQ.D 11.000
cs/nOverlay1.Q iobs/IORW1.D 11.000
cs/nOverlay1.Q iobs/Load1.D 11.000
cs/nOverlay1.Q iobs/PS_FSM_FFd2.D 11.000
cs/nOverlay1.Q nDTACK_FSB.D 11.000
cs/nOverlay1.Q ram/RAMEN.D 11.000
cs/nOverlay1.Q ram/RS_FSM_FFd1.D 11.000
cs/nOverlay1.Q ram/RS_FSM_FFd2.D 11.000
fsb/ASrf.Q fsb/Ready0r.D 11.000
fsb/ASrf.Q iobs/IORW1.D 11.000
fsb/ASrf.Q iobs/IOReady.D 11.000
fsb/ASrf.Q ram/RAMEN.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd1.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd2.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd3.D 11.000
fsb/Ready0r.Q fsb/VPA.D 11.000
fsb/Ready0r.Q nDTACK_FSB.D 11.000
fsb/Ready1r.Q fsb/Ready1r.D 11.000
iobs/IOACTr.Q iobs/IOReady.D 11.000
iobs/IORW1.Q iobs/IORW1.D 11.000
iobs/IOReady.Q fsb/Ready1r.D 11.000
iobs/IOReady.Q iobs/IOReady.D 11.000
iobs/Once.Q iobs/IOReady.D 11.000
iobs/PS_FSM_FFd1.Q iobs/IORW1.D 11.000
iobs/PS_FSM_FFd1.Q iobs/Once.D 11.000
iobs/PS_FSM_FFd1.Q iobs/PS_FSM_FFd2.D 11.000
iobs/PS_FSM_FFd2.Q iobs/IORW1.D 11.000
iobs/PS_FSM_FFd2.Q iobs/IOReady.D 11.000
iobs/PS_FSM_FFd2.Q iobs/Once.D 11.000
iobs/PS_FSM_FFd2.Q iobs/PS_FSM_FFd2.D 11.000
nADoutLE1.Q fsb/Ready1r.D 11.000
nADoutLE1.Q iobs/IOReady.D 11.000
nADoutLE1.Q iobs/Once.D 11.000
nADoutLE1.Q iobs/PS_FSM_FFd2.D 11.000
ram/BACTr.Q ram/RAMReady.D 11.000
ram/BACTr.Q ram/RASEL.D 11.000
ram/RAMEN.Q ram/RAMEN.D 11.000
ram/RAMEN.Q ram/RS_FSM_FFd1.D 11.000
ram/RAMReady.Q fsb/VPA.D 11.000
ram/RAMReady.Q nDTACK_FSB.D 11.000
ram/RS_FSM_FFd1.Q ram/RAMEN.D 11.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd1.D 11.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd3.D 11.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd1.D 11.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd2.D 11.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd3.D 11.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd2.D 11.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd3.D 11.000
ram/RefReq.Q ram/RASEL.D 11.000
ram/RefUrgent.Q ram/RASEL.D 11.000
ram/RefUrgent.Q ram/RS_FSM_FFd1.D 11.000
ram/RefUrgent.Q ram/RS_FSM_FFd2.D 11.000
ram/RefUrgent.Q ram/RS_FSM_FFd3.D 11.000
cs/nOverlay0.Q cs/nOverlay0.D 10.000
cs/nOverlay0.Q cs/nOverlay1.D 10.000
cs/nOverlay1.Q fsb/Ready0r.D 10.000
cs/nOverlay1.Q ram/RS_FSM_FFd3.D 10.000
fsb/ASrf.Q cs/nOverlay0.D 10.000
fsb/ASrf.Q cs/nOverlay1.CE 10.000
fsb/ASrf.Q fsb/Ready1r.D 10.000
fsb/ASrf.Q iobs/IOREQ.D 10.000
fsb/ASrf.Q iobs/Load1.D 10.000
fsb/ASrf.Q iobs/Once.D 10.000
fsb/ASrf.Q iobs/PS_FSM_FFd2.D 10.000
fsb/ASrf.Q nBERR_FSB.D 10.000
fsb/ASrf.Q ram/BACTr.D 10.000
fsb/ASrf.Q ram/RAMReady.D 10.000
fsb/Ready0r.Q fsb/Ready0r.D 10.000
iobs/Clear1.Q nADoutLE1.D 10.000
iobs/IOACTr.Q iobs/IOREQ.D 10.000
iobs/IOACTr.Q iobs/PS_FSM_FFd1.D 10.000
iobs/IOACTr.Q iobs/PS_FSM_FFd2.D 10.000
iobs/IOACTr.Q nBERR_FSB.D 10.000
iobs/IOL1.Q iobs/IOL0.D 10.000
iobs/IORW1.Q iobs/IORW0.D 10.000
iobs/IOU1.Q iobs/IOU0.D 10.000
iobs/Load1.Q iobs/IOL1.CE 10.000
iobs/Load1.Q iobs/IOU1.CE 10.000
iobs/Load1.Q nADoutLE1.D 10.000
iobs/Once.Q iobs/IOREQ.D 10.000
iobs/Once.Q iobs/IORW1.D 10.000
iobs/Once.Q iobs/Load1.D 10.000
iobs/Once.Q iobs/PS_FSM_FFd2.D 10.000
iobs/Once.Q nBERR_FSB.D 10.000
iobs/PS_FSM_FFd1.Q iobs/ALE0.D 10.000
iobs/PS_FSM_FFd1.Q iobs/Clear1.D 10.000
iobs/PS_FSM_FFd1.Q iobs/IOL0.CE 10.000
iobs/PS_FSM_FFd1.Q iobs/IOREQ.D 10.000
iobs/PS_FSM_FFd1.Q iobs/IOU0.CE 10.000
iobs/PS_FSM_FFd1.Q iobs/Load1.D 10.000
iobs/PS_FSM_FFd1.Q iobs/PS_FSM_FFd1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/ALE0.D 10.000
iobs/PS_FSM_FFd2.Q iobs/Clear1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/IOL0.CE 10.000
iobs/PS_FSM_FFd2.Q iobs/IOU0.CE 10.000
iobs/PS_FSM_FFd2.Q iobs/Load1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/PS_FSM_FFd1.D 10.000
iobs/PS_FSM_FFd2.Q nBERR_FSB.D 10.000
nADoutLE1.Q iobs/Clear1.D 10.000
nADoutLE1.Q iobs/IOL0.D 10.000
nADoutLE1.Q iobs/IORW1.D 10.000
nADoutLE1.Q iobs/IOU0.D 10.000
nADoutLE1.Q iobs/Load1.D 10.000
nADoutLE1.Q nADoutLE1.D 10.000
nADoutLE1.Q nBERR_FSB.D 10.000
nADoutLE1.Q nDTACK_FSB.D 10.000
nBERR_FSB.Q nBERR_FSB.D 10.000
ram/BACTr.Q ram/RAMEN.D 10.000
ram/BACTr.Q ram/RS_FSM_FFd2.D 10.000
ram/RAMEN.Q ram/RS_FSM_FFd3.D 10.000
ram/RAMReady.Q fsb/Ready0r.D 10.000
ram/RASEL.Q nCAS.D 10.000
ram/RS_FSM_FFd1.Q ram/RAMReady.D 10.000
ram/RS_FSM_FFd1.Q ram/RASEL.D 10.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd2.D 10.000
ram/RS_FSM_FFd1.Q ram/RefDone.D 10.000
ram/RS_FSM_FFd1.Q ram/RefRAS.D 10.000
ram/RS_FSM_FFd2.Q ram/RAMEN.D 10.000
ram/RS_FSM_FFd2.Q ram/RefDone.D 10.000
ram/RS_FSM_FFd2.Q ram/RefRAS.D 10.000
ram/RS_FSM_FFd3.Q ram/RAMEN.D 10.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd1.D 10.000
ram/RefDone.Q ram/RefDone.D 10.000
ram/RefDone.Q ram/RefReq.D 10.000
ram/RefDone.Q ram/RefUrgent.D 10.000
ram/RefReq.Q ram/RAMEN.D 10.000
ram/RefReq.Q ram/RS_FSM_FFd2.D 10.000
ram/RefReqSync.Q ram/RefDone.D 10.000
ram/RefReqSync.Q ram/RefReq.D 10.000
ram/RefUrgent.Q ram/RAMEN.D 10.000
ram/RegUrgentSync.Q ram/RefUrgent.D 10.000

Clock to Setup for clock C8M
Source Destination Delay
cnt/IPL2r.Q cnt/PORS_FSM_FFd1.D 10.000
cnt/IPL2r.Q nBR_IOB.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<0>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<1>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<0>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<10>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<10>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<10>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<10>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<11>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<11>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<11>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<12>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<12>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<0>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<1>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<13>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<13>.Q cnt/PORS_FSM_FFd1.D 10.000
cnt/LTimer<13>.Q cnt/PORS_FSM_FFd2.D 10.000
cnt/LTimer<13>.Q cnt/nRESout.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<1>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<1>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<2>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<2>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<3>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<3>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<4>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<4>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<5>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<5>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<6>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<6>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<7>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<7>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<8>.D 10.000
cnt/LTimer<8>.Q cnt/LTimer<9>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<10>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<11>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<12>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<13>.D 10.000
cnt/LTimer<9>.Q cnt/LTimer<9>.D 10.000
cnt/PORS_FSM_FFd1.Q cnt/PORS_FSM_FFd1.D 10.000
cnt/PORS_FSM_FFd1.Q cnt/PORS_FSM_FFd2.D 10.000
cnt/PORS_FSM_FFd1.Q cnt/nRESout.D 10.000
cnt/PORS_FSM_FFd1.Q nAoutOE.D 10.000
cnt/PORS_FSM_FFd1.Q nBR_IOB.D 10.000
cnt/PORS_FSM_FFd2.Q cnt/PORS_FSM_FFd1.D 10.000
cnt/PORS_FSM_FFd2.Q cnt/PORS_FSM_FFd2.D 10.000
cnt/PORS_FSM_FFd2.Q cnt/nRESout.D 10.000
cnt/PORS_FSM_FFd2.Q nAoutOE.D 10.000
cnt/PORS_FSM_FFd2.Q nBR_IOB.D 10.000
cnt/nRESout.Q cnt/nRESout.D 10.000
nBR_IOB.Q nAoutOE.D 10.000
nBR_IOB.Q nBR_IOB.D 10.000

Clock to Setup for clock C16M
Source Destination Delay
iobm/BERRrf.Q iobm/IOBERR.D 11.000
iobm/BERRrr.Q iobm/IOBERR.D 11.000
iobm/DTACKrf.Q iobm/IOBERR.D 11.000
iobm/DTACKrr.Q iobm/IOBERR.D 11.000
iobm/IOBERR.Q iobm/IOBERR.D 11.000
iobm/IOS_FSM_FFd1.Q iobm/IOACT.D 11.000
iobm/IOS_FSM_FFd1.Q iobm/IOBERR.D 11.000
iobm/IOS_FSM_FFd2.Q iobm/IOBERR.D 11.000
iobm/IOS_FSM_FFd3.Q iobm/IOACT.D 11.000
iobm/IOS_FSM_FFd3.Q iobm/IOBERR.D 11.000
iobm/RESrf.Q iobm/IOACT.D 11.000
iobm/RESrf.Q iobm/IOBERR.D 11.000
iobm/RESrr.Q iobm/IOACT.D 11.000
iobm/RESrr.Q iobm/IOBERR.D 11.000
iobm/BERRrf.Q iobm/IOACT.D 10.000
iobm/BERRrf.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/BERRrr.Q iobm/IOACT.D 10.000
iobm/BERRrr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/BG.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/DTACKrf.Q iobm/IOACT.D 10.000
iobm/DTACKrf.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/DTACKrr.Q iobm/IOACT.D 10.000
iobm/DTACKrr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/ES<0>.Q iobm/ES<0>.D 10.000
iobm/ES<0>.Q iobm/ES<1>.D 10.000
iobm/ES<0>.Q iobm/ES<2>.D 10.000
iobm/ES<0>.Q iobm/ES<3>.D 10.000
iobm/ES<0>.Q iobm/ES<4>.D 10.000
iobm/ES<0>.Q iobm/ETACK.D 10.000
iobm/ES<0>.Q nVMA_IOB.D 10.000
iobm/ES<1>.Q iobm/ES<0>.D 10.000
iobm/ES<1>.Q iobm/ES<1>.D 10.000
iobm/ES<1>.Q iobm/ES<2>.D 10.000
iobm/ES<1>.Q iobm/ES<3>.D 10.000
iobm/ES<1>.Q iobm/ES<4>.D 10.000
iobm/ES<1>.Q iobm/ETACK.D 10.000
iobm/ES<1>.Q nVMA_IOB.D 10.000
iobm/ES<2>.Q iobm/ES<0>.D 10.000
iobm/ES<2>.Q iobm/ES<2>.D 10.000
iobm/ES<2>.Q iobm/ES<3>.D 10.000
iobm/ES<2>.Q iobm/ES<4>.D 10.000
iobm/ES<2>.Q iobm/ETACK.D 10.000
iobm/ES<2>.Q nVMA_IOB.D 10.000
iobm/ES<3>.Q iobm/ES<0>.D 10.000
iobm/ES<3>.Q iobm/ES<2>.D 10.000
iobm/ES<3>.Q iobm/ES<3>.D 10.000
iobm/ES<3>.Q iobm/ES<4>.D 10.000
iobm/ES<3>.Q iobm/ETACK.D 10.000
iobm/ES<3>.Q nVMA_IOB.D 10.000
iobm/ES<4>.Q iobm/ES<0>.D 10.000
iobm/ES<4>.Q iobm/ES<2>.D 10.000
iobm/ES<4>.Q iobm/ES<4>.D 10.000
iobm/ES<4>.Q iobm/ETACK.D 10.000
iobm/ES<4>.Q nVMA_IOB.D 10.000
iobm/ETACK.Q iobm/IOACT.D 10.000
iobm/ETACK.Q iobm/IOBERR.D 10.000
iobm/ETACK.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/Er2.Q iobm/ES<0>.D 10.000
iobm/Er2.Q iobm/ES<1>.D 10.000
iobm/Er2.Q iobm/ES<2>.D 10.000
iobm/Er2.Q iobm/ES<3>.D 10.000
iobm/Er2.Q iobm/ES<4>.D 10.000
iobm/IOACT.Q nVMA_IOB.D 10.000
iobm/IOREQr.Q iobm/ALE0.D 10.000
iobm/IOREQr.Q iobm/IOACT.D 10.000
iobm/IOREQr.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/ALE0.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd1.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd1.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/ALE0.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOACT.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd2.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd2.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/ALE0.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/DoutOE.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd3.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nUDS_IOB.D 10.000
iobm/RESrf.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/RESrr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/VPArf.Q nVMA_IOB.D 10.000
iobm/VPArr.Q nVMA_IOB.D 10.000
iobm/nASr.Q iobm/BG.CE 10.000
nAS_IOB.Q iobm/nASr.D 10.000
nVMA_IOB.Q iobm/ETACK.D 10.000
nVMA_IOB.Q nVMA_IOB.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A_FSB<15> RA<5> 11.000
A_FSB<20> nROMCS 11.000
A_FSB<21> RA<8> 11.000
A_FSB<21> nROMCS 11.000
A_FSB<22> RA<8> 11.000
A_FSB<22> nROMCS 11.000
A_FSB<23> RA<8> 11.000
A_FSB<23> nROMCS 11.000
A_FSB<5> RA<4> 11.000
A_FSB<6> RA<5> 11.000
A_FSB<7> RA<6> 11.000
A_FSB<9> RA<8> 11.000
nAS_FSB nRAMLWE 11.000
nLDS_FSB nRAMLWE 11.000
nWE_FSB nRAMLWE 11.000
A_FSB<10> RA<0> 10.000
A_FSB<11> RA<1> 10.000
A_FSB<12> RA<2> 10.000
A_FSB<13> RA<3> 10.000
A_FSB<14> RA<4> 10.000
A_FSB<16> RA<6> 10.000
A_FSB<17> RA<7> 10.000
A_FSB<18> RA<8> 10.000
A_FSB<19> RA<11> 10.000
A_FSB<19> RA<9> 10.000
A_FSB<1> RA<0> 10.000
A_FSB<20> RA<9> 10.000
A_FSB<20> nDinOE 10.000
A_FSB<21> RA<10> 10.000
A_FSB<21> nDinOE 10.000
A_FSB<21> nRAS 10.000
A_FSB<22> nDinOE 10.000
A_FSB<22> nRAS 10.000
A_FSB<23> nDinOE 10.000
A_FSB<23> nRAS 10.000
A_FSB<2> RA<1> 10.000
A_FSB<3> RA<2> 10.000
A_FSB<4> RA<3> 10.000
A_FSB<8> RA<7> 10.000
nAS_FSB nDinOE 10.000
nAS_FSB nOE 10.000
nAS_FSB nRAMUWE 10.000
nAS_FSB nRAS 10.000
nAS_FSB nROMWE 10.000
nAS_FSB nVPA_FSB 10.000
nUDS_FSB nRAMUWE 10.000
nWE_FSB nDinOE 10.000
nWE_FSB nOE 10.000
nWE_FSB nRAMUWE 10.000
nWE_FSB nROMWE 10.000



Number of paths analyzed: 400
Number of Timing errors: 0
Analysis Completed: Sat Mar 25 00:05:47 2023