Summary

• The Design Name
• The Fitting Status, which is one of  the following:
• Successful
• Design Rule Checking Failed
• Placement Failed
• Routing Failed
• The Software Version 
• The Device Used, with a link to a PDF version of the device documentation
• The Date and time of completion

• The number and percentage of macrocells used vs total in device 
• The number and percentage of product terms used vs total in device 
• The number and percentage of registers used vs total in device 
• The number and percentage of pins used vs total in device 
• The number and percentage of function block inputs used vs total in device 

• The first table indicates the requirements of the design, broken up by Signal Type. The number required and the number mapped onto the device are indicated for each signal type.
• The second table gives the total number of each pin type available in the device, alongwith the number used.

• Each row lists the local control term mapping for each of the eight control terms, LCT0-LCT7, in a function block.
• The control term mapping can be:
• ce - clock enable
• clk - clock
• ee - output enable
• sr - set/reset
• uct1 - universal control term clock
• uct2 - universal control term output enable
• uct3 - universal control term set
• uct4 - universal control term reset
• Each LCT can have some subset of the signals above mapped onto them:
• LCT0 - sr, oe
• LCT1 - sr, oe
• LCT2 - sr, oe
• LCT3 - sr
• LCT4 - ce, clk, sr
• LCT5 - clk, sr
• LCT6 - clk, oe
• LCT7 - clk, uct1/uct2/uct3/uct4

XC9500/XL/XV only - The Power Data table indicates the number of macrocells in standard and low power mode.

XPLA3 only - The Block Resources table indicates the number of function block control terms used vs available and the number of foldback NANDs used vs available.