Release 14.7 - xst P.20131013 (nt) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.87 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.89 secs --> Reading design: MXSE.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "MXSE.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "MXSE" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : MXSE Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "../RAM.v" in library work Compiling verilog file "../IOBS.v" in library work Module compiled Compiling verilog file "../IOBM.v" in library work Module compiled Compiling verilog file "../FSB.v" in library work Module compiled Compiling verilog file "../CS.v" in library work Module compiled Compiling verilog file "../CNT.v" in library work Module compiled Compiling verilog file "../MXSE.v" in library work Module compiled Module compiled No errors in compilation Analysis of file <"MXSE.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "../CS.v". Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../RAM.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 18 | | Inputs | 6 | | Outputs | 9 | | Clock | CLK (rising_edge) | | Power Up State | 000 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 6 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../IOBS.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 10 | | Inputs | 5 | | Outputs | 5 | | Clock | CLK (rising_edge) | | Power Up State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 9 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../IOBM.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 15 | | Inputs | 6 | | Outputs | 8 | | Clock | C16M (rising_edge) | | Power Up State | 000 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 5-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 20 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../CNT.v". Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is "../FSB.v". Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../MXSE.v". Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 2 5-bit up counter : 1 8-bit up counter : 1 # Registers : 58 1-bit register : 58 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with johnson encoding. ------------------- State | Encoding ------------------- 000 | 0000 001 | 0001 010 | 0011 011 | 0111 100 | 1111 101 | 1110 110 | 1100 111 | 1000 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with johnson encoding. ------------------- State | Encoding ------------------- 00 | 00 11 | 01 10 | 11 01 | 10 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with user encoding. ------------------- State | Encoding ------------------- 000 | 000 010 | 010 101 | 101 001 | 001 011 | 011 100 | 100 111 | 111 110 | 110 ------------------- ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 3 # Counters : 2 5-bit up counter : 1 8-bit up counter : 1 # Registers : 38 Flip-Flops : 38 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : nOverlay0 implementation constraint: INIT=r : nOverlay1 Optimizing unit ... implementation constraint: INIT=r : RAMReady implementation constraint: INIT=r : RASEL implementation constraint: INIT=r : RAMDIS1 implementation constraint: INIT=r : RefRAS implementation constraint: INIT=r : RAMDIS2 implementation constraint: INIT=r : Once implementation constraint: INIT=r : RS_FSM_FFd1 implementation constraint: INIT=r : RS_FSM_FFd2 implementation constraint: INIT=r : RS_FSM_FFd3 Optimizing unit ... implementation constraint: INIT=r : IOACTr implementation constraint: INIT=r : PS_FSM_FFd2 implementation constraint: INIT=r : Once implementation constraint: INIT=r : PS_FSM_FFd1 Optimizing unit ... implementation constraint: INIT=r : ASrf Optimizing unit ... implementation constraint: INIT=r : IOREQr implementation constraint: INIT=r : ETACK implementation constraint: INIT=r : IOS_FSM_FFd1 implementation constraint: INIT=r : IOS_FSM_FFd2 implementation constraint: INIT=r : IOS_FSM_FFd3 implementation constraint: INIT=r : IOS_FSM_FFd4 Optimizing unit ... implementation constraint: INIT=r : RefDone implementation constraint: INIT=r : RefCnt_7 implementation constraint: INIT=r : RefCnt_6 implementation constraint: INIT=r : RefCnt_5 implementation constraint: INIT=r : RefCnt_4 implementation constraint: INIT=r : RefCnt_3 implementation constraint: INIT=r : RefCnt_2 implementation constraint: INIT=r : RefCnt_1 implementation constraint: INIT=r : RefCnt_0 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : MXSE.ngr Top Level Output File Name : MXSE Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 67 Cell Usage : # BELS : 607 # AND2 : 169 # AND3 : 25 # AND4 : 14 # AND6 : 2 # AND7 : 1 # AND8 : 3 # GND : 6 # INV : 256 # OR2 : 108 # OR3 : 9 # OR4 : 1 # VCC : 1 # XOR2 : 12 # FlipFlops/Latches : 80 # FD : 54 # FDCE : 26 # IO Buffers : 67 # IBUF : 35 # OBUF : 32 ========================================================================= Total REAL time to Xst completion: 27.00 secs Total CPU time to Xst completion: 27.11 secs --> Total memory usage is 204052 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)