Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/CNT.v" into library work Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/CS.v" into library work Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/FSB.v" into library work Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/IOBM.v" into library work Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/IOBS.v" into library work Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.v" into library work Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/RAM.v" into library work