Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib uni9000_ver -lib aim_ver -lib cpld_ver -lib xilinxcorelib_ver -o C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/t_cs_isim_beh.exe -prj C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/t_cs_beh.prj work.t_cs work.glbl 
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16 
Determining compilation order of HDL files
Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/../CS.v" into library work
Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/../test/t_cs.v" into library work
Analyzing Verilog file "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Compiling module CS
Compiling module t_cs
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 3 Verilog Units
Built simulation executable C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/t_cs_isim_beh.exe
Fuse Memory Usage: 29568 KB
Fuse CPU Usage: 280 ms