Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.31 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.33 secs --> Reading design: WarpSE.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "WarpSE.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "WarpSE" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : WarpSE Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "../RAM.v" in library work Compiling verilog file "../IOBS.v" in library work Module compiled Compiling verilog file "../IOBM.v" in library work Module compiled Compiling verilog file "../FSB.v" in library work Module compiled Compiling verilog file "../CS.v" in library work Module compiled Compiling verilog file "../CNT.v" in library work Module compiled Compiling verilog file "../WarpSE.v" in library work Module compiled Module compiled No errors in compilation Analysis of file <"WarpSE.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "../CS.v". Found 1-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is "../RAM.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 14 | | Inputs | 6 | | Outputs | 8 | | Clock | CLK (rising_edge) | | Power Up State | 000 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 9 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../IOBS.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 10 | | Inputs | 5 | | Outputs | 5 | | Clock | CLK (rising_edge) | | Power Up State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 10 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../IOBM.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 13 | | Inputs | 5 | | Outputs | 7 | | Clock | C16M (rising_edge) | | Power Up State | 000 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 15 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../CNT.v". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 8 | | Inputs | 2 | | Outputs | 5 | | Clock | CLK (rising_edge) | | Power Up State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 2-bit adder for signal <$add0000> created at line 67. Found 12-bit adder for signal <$add0001> created at line 68. Found 2-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit up counter for signal . Found 1-bit register for signal . Found 4-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 11 D-type flip-flop(s). inferred 2 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "../FSB.v". Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "../WarpSE.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Summary: inferred 5 Tristate(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 2 12-bit adder : 1 2-bit adder : 1 # Counters : 3 4-bit up counter : 3 # Registers : 68 1-bit register : 67 2-bit register : 1 # Tristates : 5 1-bit tristate buffer : 5 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with johnson encoding. ------------------- State | Encoding ------------------- 00 | 00 01 | 01 10 | 11 11 | 10 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with one-hot encoding. ------------------- State | Encoding ------------------- 000 | 0000001 010 | 0000010 011 | 0000100 100 | 0001000 101 | 0010000 110 | 0100000 111 | 1000000 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with johnson encoding. ------------------- State | Encoding ------------------- 00 | 00 11 | 01 10 | 11 01 | 10 ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with one-hot encoding. ------------------- State | Encoding ------------------- 000 | 00000001 100 | 00000010 001 | 00000100 010 | 00001000 011 | 00010000 101 | 00100000 110 | 01000000 111 | 10000000 ------------------- ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 4 # Adders/Subtractors : 2 12-bit adder : 1 2-bit adder : 1 # Counters : 3 4-bit up counter : 3 # Registers : 48 Flip-Flops : 48 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : nOverlay Optimizing unit ... implementation constraint: INIT=s : RS_FSM_FFd8 implementation constraint: INIT=r : RASEL implementation constraint: INIT=r : RASrr implementation constraint: INIT=r : RASEN implementation constraint: INIT=r : RS_FSM_FFd1 implementation constraint: INIT=r : RS_FSM_FFd2 implementation constraint: INIT=r : RS_FSM_FFd3 implementation constraint: INIT=r : RS_FSM_FFd4 implementation constraint: INIT=r : RS_FSM_FFd5 implementation constraint: INIT=r : RS_FSM_FFd6 implementation constraint: INIT=r : RS_FSM_FFd7 implementation constraint: INIT=r : RASrf Optimizing unit ... implementation constraint: INIT=r : IOACTr implementation constraint: INIT=r : TS_FSM_FFd2 implementation constraint: INIT=r : Sent implementation constraint: INIT=r : TS_FSM_FFd1 Optimizing unit ... implementation constraint: INIT=r : ASrf Optimizing unit ... implementation constraint: INIT=s : IOS_FSM_FFd7 implementation constraint: INIT=r : DoutOE implementation constraint: INIT=r : IOS_FSM_FFd6 implementation constraint: INIT=r : IOS_FSM_FFd1 implementation constraint: INIT=r : IOS_FSM_FFd2 implementation constraint: INIT=r : IOS_FSM_FFd3 implementation constraint: INIT=r : IOS_FSM_FFd4 implementation constraint: INIT=r : IOS_FSM_FFd5 Optimizing unit ... implementation constraint: INIT=r : Timer_1 implementation constraint: INIT=r : IS_FSM_FFd2 implementation constraint: INIT=r : IS_FSM_FFd1 implementation constraint: INIT=r : Timer_2 implementation constraint: INIT=r : Timer_0 implementation constraint: INIT=r : WS_3 implementation constraint: INIT=r : WS_0 implementation constraint: INIT=r : WS_1 implementation constraint: INIT=r : WS_2 implementation constraint: INIT=r : Timer_3 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : WarpSE.ngr Top Level Output File Name : WarpSE Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 75 Cell Usage : # BELS : 672 # AND2 : 211 # AND3 : 29 # AND4 : 12 # AND5 : 2 # AND7 : 2 # AND8 : 4 # GND : 6 # INV : 262 # OR2 : 105 # OR3 : 14 # OR4 : 4 # VCC : 1 # XOR2 : 20 # FlipFlops/Latches : 100 # FD : 68 # FDC : 2 # FDCE : 29 # FDP : 1 # IO Buffers : 70 # IBUF : 35 # IOBUFE : 1 # OBUF : 30 # OBUFE : 4 ========================================================================= Total REAL time to Xst completion: 6.00 secs Total CPU time to Xst completion: 5.44 secs --> Total memory usage is 266948 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 3 ( 0 filtered) Number of infos : 0 ( 0 filtered)