35 lines
1.0 KiB
Verilog
35 lines
1.0 KiB
Verilog
module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output reg nVPA,
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/* AS cycle detection */
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output BACT, output BACTr_out, output reg WS,
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/* Ready inputs */
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input ROMCS,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input QoSReady,
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/* Interrupt acknowledge select */
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input IACS);
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/* AS cycle detection */
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reg ASrf = 0;
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reg [3:1] BACTr;
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always @(negedge FCLK) begin ASrf <= !nAS; end
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assign BACT = !nAS || ASrf; // BACT - bus active
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assign BACTr_out = BACTr[1];
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always @(posedge FCLK) BACTr[3:1] <= { BACTr[2:1], BACT };
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always @(posedge FCLK) WS <= BACTr[3:1]==3'b111 && BACT;
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/* DTACK/VPA control */
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wire Ready = QoSReady && (
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(RAMCS && RAMReady && !IOPWCS) ||
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(RAMCS && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS) || (IONPReady));
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else nVPA <= !(Ready && BACT && IACS);
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end
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endmodule
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