121 lines
3.0 KiB
Verilog
121 lines
3.0 KiB
Verilog
module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
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input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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input IORDREQ, input IOWRREQ, input IOLDS, input IOUDS,
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output reg IOACT, output reg IODONE, output reg IOBERR);
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/* C8M clock registration */
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reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
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/* I/O request input synchronization */
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reg IORDREQr; always @(posedge C16M) IORDREQr <= IORDREQ;
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reg IOWRREQr; always @(posedge C16M) IOWRREQr <= IOWRREQ;
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wire IOREQr = IORDREQr || IOWRREQr;
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/* VPA synchronization */
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reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
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/* E clock synchronization */
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reg Er; always @(negedge C8M) begin Er <= E; end
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/* E clock state */
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reg [3:0] ES;
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always @(negedge C8M) begin
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if (!E && Er) ES <= 1;
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else if (ES==0 || ES==9) ES <= 0;
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else ES <= ES+1;
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end
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/* ETACK and VMA generation */
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wire ETACK = (ES==8) && !nVMA;
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always @(posedge C8M) begin
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if ((ES==5) && IOACT && VPAr) nVMA <= 0;
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else if(ES==0) nVMA <= 1;
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end
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/* DTACK and BERR synchronization */
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always @(negedge C8M, posedge nASout) begin
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if (nASout) begin
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IODONE <= 0;
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IOBERR <= 0;
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end else begin
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IODONE <= (!nDTACK || ETACK || !nRES);
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IOBERR <= !nBERR;
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end
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end
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/* I/O bus state */
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reg [2:0] IOS = 0;
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reg IOS0;
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always @(posedge C16M) begin
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if (IOS==0) begin
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if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
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IOS <= 2;
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IOS0 <= 0;
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end else begin // "regular" IOS0
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IOS <= 0;
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IOS0 <= 1;
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end
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IOACT <= IOREQr && AoutOE;
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ALE0 <= IOREQr && AoutOE;
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end else if (IOS==2) begin
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IOS <= 3;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==3) begin
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IOS <= 4;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==4) begin
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IOS <= 5;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==5) begin
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if (!C8Mr && (IODONE || IOBERR)) begin
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IOS <= 6;
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IOACT <= 0;
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end else begin
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IOS <= 5;
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IOACT <= 1;
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end
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IOS0 <= 0;
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ALE0 <= 1;
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end else if (IOS==6) begin
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IOS <= 7;
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IOS0 <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end else if (IOS==7) begin
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IOS <= 0;
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IOS0 <= 1;
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IOACT <= 0;
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ALE0 <= 0;
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end
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end
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/* PDS address and data latch control */
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always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
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reg DoutOE = 0;
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always @(posedge C16M) begin
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DoutOE <= (IOS==0 && IOWRREQr && !C8Mr) ||
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(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
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end
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assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
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/* AS, DS control */
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always @(negedge C16M) begin
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nASout <= !((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
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nLDS <= !(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nLDS) || IOS==3 || IOS==4 || IOS==5));
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nUDS <= !(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nUDS) || IOS==3 || IOS==4 || IOS==5));
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end
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endmodule
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