101 lines
1.6 KiB
Verilog
101 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 07:17:58 10/23/2021
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// Design Name: CS
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// Module Name: C:/Users/zanek/Documents/GitHub/SE-030/cpld/test/t_cs.v
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// Project Name: MXSE
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: CS
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module t_cs;
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// Inputs
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reg [23:8] A;
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reg CLK;
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reg nRES;
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reg nWE;
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reg CACT;
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// Outputs
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wire IOCS;
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wire IACS;
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wire ROMCS;
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wire RAMCS;
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wire SndRAMCSWR;
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// Instantiate the Unit Under Test (UUT)
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CS uut (
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.A(A),
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.CLK(CLK),
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.nRES(nRES),
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.nWE(nWE),
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.CACT(CACT),
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.IOCS(IOCS),
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.IACS(IACS),
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.ROMCS(ROMCS),
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.RAMCS(RAMCS),
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.SndRAMCSWR(SndRAMCSWR)
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);
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initial begin
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A = 0;
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CLK = 0;
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nRES = 0;
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nWE = 0;
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CACT = 0;
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#0;
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CLK = 0; #25;
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CLK = 1; #5;
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nRES = 1; #20;
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CLK = 0; #25;
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CLK = 1; #25;
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A = 16'h0000; #50;
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A = 16'h5000; #50;
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A = 16'h6000; #50;
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A = 16'h7F00; #50;
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A = 16'h7FA1; #50;
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A = 16'h7FA2; #50;
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A = 16'h4000; #50;
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CLK = 0; #25;
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CLK = 1; #5;
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CACT = 1; #20;
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CLK = 0; #25;
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CLK = 1; #5;
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CACT = 0; #20;
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CLK = 0; #25;
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CLK = 1; #25;
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A = 16'h0000; #50;
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A = 16'h5000; #50;
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A = 16'h6000; #50;
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A = 16'h0000; #50;
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A = 16'h3FA1; #50;
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A = 16'h3FA2; #50;
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A = 16'h4000; #50;
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end
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endmodule
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