124 lines
1.8 KiB
Verilog
124 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 07:10:03 10/23/2021
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// Design Name: FSB
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// Module Name: C:/Users/zanek/Documents/GitHub/SE-030/cpld/test/t_fsb_dtack.v
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// Project Name: MXSE
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: FSB
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module t_fsb_dtack;
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// Inputs
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reg FCLK;
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reg nAS;
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reg Ready;
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reg IACS;
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// Outputs
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wire nDTACK;
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wire nVPA;
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wire AINACT;
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wire BACT;
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wire CACT;
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// Instantiate the Unit Under Test (UUT)
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FSB uut (
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.FCLK(FCLK),
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.nAS(nAS),
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.nDTACK(nDTACK),
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.nVPA(nVPA),
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.AINACT(AINACT),
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.BACT(BACT),
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.CACT(CACT),
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.Ready(Ready),
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.IACS(IACS)
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);
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initial begin
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FCLK = 0;
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nAS = 1;
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Ready = 1;
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IACS = 0;
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#0;
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FCLK = 0; #25;
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FCLK = 1; #5;
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nAS = 1'bX; #20;
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nAS = 0;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #5;
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nAS = 1'bX; #20;
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nAS = 1;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #5;
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nAS = 1'bX; #20;
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nAS = 0;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #5;
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nAS = 1'bX; #20;
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nAS = 1;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #5;
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Ready = 0; nAS = 1'bX; #20;
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nAS = 0;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #5;
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Ready = 1; #20;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #5;
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nAS = 1'bX; #20;
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nAS = 1;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #25;
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FCLK = 0; #25;
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FCLK = 1; #25;
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end
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endmodule
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