114 lines
3.4 KiB
Verilog
114 lines
3.4 KiB
Verilog
module CS(
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/* MC68HC000 interface */
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input [23:08] A, input CLK, input nRES, input nWE,
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/* AS cycle detection */
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input BACT,
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/* Device select outputs */
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output IOCS, output IOPWCS, output IACS,
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output ROMCS, output ROMCS4X,
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output RAMCS, output RAMCS0X, output SndRAMCSWR);
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/* Overlay control */
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reg nOverlay = 0; wire Overlay = !nOverlay;
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reg ODCSr;
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always @(posedge CLK) begin
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ODCSr <= ROMCS4X && BACT;
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if (!BACT) begin
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if (!nRES) nOverlay <= 0;
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else if (ODCSr) nOverlay <= 1;
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end
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end
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/* ROM select signals */
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assign ROMCS4X = A[23:20]==4'h4;
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assign ROMCS = ((A[23:20]==4'h0) && Overlay) || ROMCS4X;
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/* RAM select signals */
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assign RAMCS0X = A[23:22]==2'b00;
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assign RAMCS = RAMCS0X && !Overlay;
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wire VidRAMCSWR64k = RAMCS0X && !nWE && (A[23:20]==4'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF
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wire VidRAMCSWR = VidRAMCSWR64k && (
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(A[15:12]==4'h2 && // 1792 bytes RAM, 2304 bytes video
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(A[11:8]==4'h7 ||
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A[11:8]==4'h8 ||
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A[11:8]==4'h9 ||
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A[11:8]==4'hA ||
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A[11:8]==4'hB ||
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A[11:8]==4'hC ||
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A[11:8]==4'hD ||
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A[11:8]==4'hE ||
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A[11:8]==4'hF)) ||
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(A[15:12]==4'h3) || // 4096 bytes video
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(A[15:12]==4'h4) || // 4096 bytes video
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(A[15:12]==4'h5) || // 4096 bytes video
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(A[15:12]==4'h6) || // 4096 bytes video
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(A[15:12]==4'h7 && // 3200 bytes video, 896 bytes RAM
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(A[11:8]==4'h0 ||
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A[11:8]==4'h1 ||
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A[11:8]==4'h2 ||
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A[11:8]==4'h3 ||
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A[11:8]==4'h4 ||
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A[11:8]==4'h5 ||
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A[11:8]==4'h6 ||
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A[11:8]==4'h7 ||
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A[11:8]==4'h8 ||
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A[11:8]==4'h9 ||
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A[11:8]==4'hA ||
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A[11:8]==4'hB ||
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A[11:8]==4'hC)) ||
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(A[15:12]==4'hA && // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
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(A[11:8]==4'h1 ||
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A[11:8]==4'h2 ||
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A[11:8]==4'h3 ||
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A[11:8]==4'h7 ||
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A[11:8]==4'h8 ||
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A[11:8]==4'h9 ||
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A[11:8]==4'hA ||
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A[11:8]==4'hB ||
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A[11:8]==4'hC ||
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A[11:8]==4'hD ||
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A[11:8]==4'hE ||
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A[11:8]==4'hF)) ||
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(A[15:12]==4'hB) || // 4096 bytes video
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(A[15:12]==4'hC) || // 4096 bytes video
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(A[15:12]==4'hD) || // 4096 bytes video
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(A[15:12]==4'hE) || // 4096 bytes video
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(A[15:12]==4'hF && // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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(A[11:8]==4'h0 ||
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A[11:8]==4'h1 ||
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A[11:8]==4'h2 ||
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A[11:8]==4'h3 ||
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A[11:8]==4'h4 ||
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A[11:8]==4'h5 ||
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A[11:8]==4'h6 ||
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A[11:8]==4'h7 ||
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A[11:8]==4'h8 ||
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A[11:8]==4'h9 ||
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A[11:8]==4'hA ||
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A[11:8]==4'hB ||
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A[11:8]==4'hC ||
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A[11:8]==4'hD ||
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A[11:8]==4'hE ||
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A[11:8]==4'hF)));
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assign SndRAMCSWR = VidRAMCSWR64k && (
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((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) ||
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((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
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/* Select signals - IOB domain */
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assign IACS = (A[23:20]==4'hF) && (A[19:18]==2'b11); // IACK
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assign IOCS = (A[23:20]==4'hF) || // IACK
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(A[23:20]==4'hE) || // VIA
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(A[23:20]==4'hD) || // IWM
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(A[23:20]==4'hC) || // empty / fast ROM
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(A[23:20]==4'hB) || // SCC write
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(A[23:20]==4'hA) || // empty
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(A[23:20]==4'h9) || // SCC read/reset
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(A[23:20]==4'h8) || // empty
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(A[23:20]==4'h7) || // empty
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(A[23:20]==4'h6) || // empty
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(A[23:20]==4'h5) || // SCSI
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((A[23:20]==4'h4) && Overlay) || // ROM once
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VidRAMCSWR; // Write to video RAM
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assign IOPWCS = VidRAMCSWR;
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endmodule
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