mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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68 lines
2.6 KiB
Verilog
68 lines
2.6 KiB
Verilog
module CS(
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/* Setting input */
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input MotherboardROMEN,
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/* MC68HC000 interface */
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input [23:08] A, input CLK, input nRES, input nWE,
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/* AS cycle detection */
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input BACT,
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/* Device select outputs */
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output IOCS, output SCSICS, output IOPWCS, output IACS, output ROMCS, output RAMCS, output SndRAMCSWR);
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/* Overlay control */
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reg nOverlay0 = 0;
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reg nOverlay1 = 0;
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wire Overlay = ~nOverlay1;
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wire ODCS = A[23:20]==4'h4; // Disable overlay
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always @(posedge CLK, negedge nRES) begin
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if (~nRES) nOverlay0 <= 0;
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else if (BACT && ODCS) nOverlay0 <= 1;
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end
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always @(posedge CLK) begin
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if (~BACT) nOverlay1 <= nOverlay0;
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end
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/* Select signals - FSB domain */
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wire RAMCS_OverlayOff = A[23:22]==2'b00;
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wire RAMCS_OverlayOn = A[23:21]==3'b011;
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assign RAMCS = (RAMCS_OverlayOff && ~Overlay) || // 000000-3FFFFF when overlay disabled
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(RAMCS_OverlayOn && Overlay); // 600000-7FFFFF when overlay enabled
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wire VidRAMCSWR64k = RAMCS && A[21:20]==2'h3 && A[19:16]==4'hF && ~nWE; // 3F0000-3FFFFF / 7F0000-7FFFFF
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wire VidRAMCSWR = VidRAMCSWR64k && (
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(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
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(A[15:12]==4'h3) || // 4096 bytes video
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(A[15:12]==4'h4) || // 4096 bytes video
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(A[15:12]==4'h5) || // 4096 bytes video
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(A[15:12]==4'h6) || // 4096 bytes video
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(A[15:12]==4'h7) || // 3200 bytes video, 896 bytes RAM,
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(A[15:12]==4'hA) || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
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(A[15:12]==4'hB) || // 4096 bytes video
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(A[15:12]==4'hC) || // 4096 bytes video
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(A[15:12]==4'hD) || // 4096 bytes video
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(A[15:12]==4'hE) || // 4096 bytes video
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(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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assign SndRAMCSWR = VidRAMCSWR64k && (
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(A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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(A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign ROMCS = (A[23:20]==4'h4 && !MotherboardROMEN) ||
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(A[23:20]==4'h8 && MotherboardROMEN) ||
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(A[23:20]==4'h0 && Overlay);
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/* Select signals - IOB domain */
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assign IACS = A[23:08]==16'hFFFF; // IACK
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assign IOCS = (A[23:20]==4'h4 && MotherboardROMEN) || // Motherboard ROM
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A[23:20]==4'h5 || // SCSI
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A[23:20]==4'h8 || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'hA || // empty
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A[23:20]==4'hB || // SCC write
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A[23:20]==4'hC || // empty
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hF || // IACK
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VidRAMCSWR;
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assign SCSICS = A[23:20]==4'h5; // SCSI
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assign IOPWCS = RAMCS_OverlayOff && ~nWE;
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endmodule
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