155 lines
3.7 KiB
Verilog
155 lines
3.7 KiB
Verilog
module MXSE(
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input [23:1] A_FSB,
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input nAS_FSB,
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input nLDS_FSB,
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input nUDS_FSB,
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input nWE_FSB,
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output nDTACK_FSB,
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output nVPA_FSB,
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output nBERR_FSB,
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input CLK_FSB,
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input CLK2X_IOB,
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input CLK_IOB,
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input E_IOB,
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input nDTACK_IOB,
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input nVPA_IOB,
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output nVMA_IOB,
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output nAS_IOB,
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output nUDS_IOB,
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output nLDS_IOB,
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output nBR_IOB,
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input nBG_IOB,
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input nBERR_IOB,
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input nRES,
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input nIPL2,
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output nROMCS,
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output nRAMLWE,
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output nRAMUWE,
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output nROMWE,
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output nRAS,
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output nCAS,
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output [11:0] RA,
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output nOE,
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output nADoutLE0,
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output nADoutLE1,
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output nAoutOE,
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output nDoutOE,
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output nDinOE,
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output nDinLE,
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input [2:0] SW,
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output CLK20EN,
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output CLK25EN);
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/* DIP switches */
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assign CLK20EN = SW[0];
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assign CLK25EN = !SW[0];
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wire MotherboardROMEN = !SW[1];
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/* AS cycle detection */
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wire BACT;
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/* Refresh request/ack signals */
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wire RefReq, RefUrgent, RefAck;
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wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR;
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CS cs(
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/* Setting input */
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MotherboardROMEN,
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/* MC68HC000 interface */
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A_FSB[23:08], CLK_FSB, nRES, nWE_FSB,
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/* AS cycle detection */
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BACT,
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/* Device select outputs */
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IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR);
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wire Ready_RAM;
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RAM ram(
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/* MC68HC000 interface */
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CLK_FSB, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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/* AS cycle detection */
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BACT,
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/* Select and ready signals */
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RAMCS, ROMCS, Ready_RAM,
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/* Refresh Counter Interface */
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RefReq, RefUrgent, RefAck,
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/* DRAM and NOR flash interface */
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RA[11:0], nRAS, nCAS,
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nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
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wire Ready_IOBS, BERR_IOBS;
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wire Park, IOREQ, IOACT, IOBERR;
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wire ALE0S, ALE0M, ALE1;
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assign nADoutLE0 = ~(ALE0S || ALE0M);
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assign nADoutLE1 = ~ALE1;
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wire IORW0, IOL0, IOU0;
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IOBS iobs(
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/* MC68HC000 interface */
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CLK_FSB, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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/* AS cycle detection, FSB BERR */
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BACT,
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/* Select and ready signals */
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IOCS, IOPWCS, Ready_IOBS, BERR_IOBS,
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/* Read data OE control */
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nDinOE,
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/* IOB Master Controller Interface */
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IOREQ, IOACT, IOBERR,
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/* FIFO primary level control */
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ALE0S, IORW0, IOL0, IOU0,
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/* FIFO secondary level control */
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ALE1);
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wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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assign nAS_IOB = nAoutOE ? 1'bZ : nAS_IOBout;
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assign nLDS_IOB = nAoutOE ? 1'bZ : nLDS_IOBout;
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assign nUDS_IOB = nAoutOE ? 1'bZ : nUDS_IOBout;
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assign nVMA_IOB = nAoutOE ? 1'bZ : nVMA_IOBout;
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IOBM iobm(
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/* PDS interface */
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CLK2X_IOB, CLK_IOB, E_IOB,
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nBR_IOB, nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
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nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRES,
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/* PDS address and data latch control */
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nAoutOE, nDoutOE, ALE0M, nDinLE,
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/* IO bus slave port interface */
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IOACT, IOBERR,
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Park, IOREQ, IOL0, IOU0, IORW0);
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wire TimeoutA, TimeoutB;
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CNT cnt(
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/* FSB clock and AS detection */
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CLK_FSB, BACT,
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/* Refresh request */
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RefReq, RefUrgent, RefAck,
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/* Timeout signals */
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TimeoutA, TimeoutB);
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/* Accelerator Disable Control */
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reg RESr0 = 0;
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reg RESr1 = 0;
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reg RESr2 = 0;
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reg IPL2r0 = 0;
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reg IPL2r1 = 0;
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reg RESDone = 0;
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reg Disable = 0;
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assign Park = ~Disable;
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always @(posedge CLK_FSB) begin
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RESr0 <= ~nRES; RESr1 <= RESr0; RESr2 <= RESr1;
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IPL2r0 <= ~nIPL2; IPL2r1 <= IPL2r0;
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if ( RESr0 && RESr1 && RESr2 && ~RESDone && IPL2r0 && IPL2r1) Disable <= 1;
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if (~RESr0 && ~RESr1 && RESr2) RESDone <= 1;
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end
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FSB fsb(
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/* MC68HC000 interface */
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CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB,
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/* AS cycle detection */
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BACT,
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/* Ready and IA inputs */
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Ready_RAM, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable,
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/* BERR inputs */
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(~SCSICS && TimeoutB), BERR_IOBS,
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/* Interrupt acknowledge select */
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IACS);
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endmodule
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