144 lines
3.9 KiB
Verilog
144 lines
3.9 KiB
Verilog
module IOBS(
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/* MC68HC000 interface */
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input CLK, input nWE, input nAS, input nLDS, input nUDS,
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/* AS cycle detection */
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input BACT,
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/* Select signals */
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input IOCS, input IOPWCS, input ROMCS,
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/* FSB cycle termination outputs */
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output IOBS_Ready, output reg nBERR_FSB,
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/* Read data OE control */
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output nDinOE,
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/* IOB Master Controller Interface */
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output reg IOREQ, input IOACT, input IOBERR,
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/* FIFO primary level control */
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output reg ALE0, output reg IORW0, output reg IOL0, output reg IOU0,
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/* FIFO secondary level control */
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output reg ALE1);
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/* IOACT input synchronization */
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reg IOACTr = 0;
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always @(posedge CLK) begin IOACTr <= IOACT; end
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/* Read data OE control */
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assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
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/* I/O transfer state
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* TS0 - I/O bridge idle:
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* asserts IOREQ
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* transitions to TS3 when BACT && IOCS && !ALE1 && !Sent true
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* TS3 - starting I/O transfer:
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latches LDS and UDS from FSB or FIFO secondary level
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transitions immediately to TS2
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* TS2 - waiting for IOBM to begin:
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transitions to TS1 when IOACT true
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* TS1 - waiting for IOBM to finish:
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* transitions to TS1 when IOACT false */
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reg [1:0] TS = 0;
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reg Sent = 0;
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/* FIFO second level control */
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reg Load1;
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reg Clear1;
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reg IORW1;
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reg IOL1;
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reg IOU1;
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always @(posedge CLK) begin
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// If write currently posting (TS!=0),
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// I/O selected, and FIFO secondary level empty
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if (TS!=0 && BACT && IOCS && !ALE1 && !Sent && IOPWCS) begin
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// Latch R/W now but latch address and LDS/UDS next cycle
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IORW1 <= nWE;
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Load1 <= 1;
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end else Load1 <= 0;
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end
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always @(posedge CLK) begin
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// Make address latch transparent in cycle after TS3
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// (i.e. first TS2 cycle that's not part of current write)
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if (TS==3) Clear1 <= 1;
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else Clear1 <= 0;
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end
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always @(posedge CLK) begin
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if (Load1) begin
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// Latch address, LDS, UDS when Load1 true
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ALE0 <= 1;
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IOL1 <= ~nLDS;
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IOU1 <= ~nUDS;
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end else if (Clear1) ALE1 <= 0;
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end
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/* FIFO Primary Level Control */
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always @(posedge CLK) begin
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if (TS==0) begin
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if (ALE1) begin // If FIFO secondary level occupied
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// Request transfer from IOBM and latch R/W from FIFO
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TS <= 3;
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IOREQ <= 1;
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IORW0 <= IORW1;
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end else if (BACT && IOCS && !ALE1 && !Sent) begin // If I/O selected and FIFO empty
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// Request transfer from IOBM and latch R/W from FSB
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TS <= 3;
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IOREQ <= 1;
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IORW0 <= nWE;
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end else begin // Otherwise stay in idle
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TS <= 0;
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IOREQ <= 0;
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end
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ALE0 <= 0;
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end else if (TS==3) begin
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// Always go to TS2. Keep IOREQ active
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TS <= 2;
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IOREQ <= 1;
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// Latch address (and data)
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ALE0 <= 1;
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// Latch data strobes from FIFO or FSB as appropriate
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if (ALE1) begin
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else begin
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IOL0 <= ~nLDS;
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IOU0 <= ~nUDS;
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end
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end else if (TS==2) begin
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// Wait for IOACT then withdraw IOREQ and enter TS1
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if (IOACTr) begin
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TS <= 1;
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IOREQ <= 0;
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end else begin
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TS <= 2;
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IOREQ <= 1;
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end
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ALE0 <= 1;
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end else if (TS==1) begin
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// Wait for IOACT low (transfer over) before going back to idle
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if (~IOACTr) TS <= 0;
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else TS <= 1;
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IOREQ <= 0;
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// Address latch released since it's controlled by IOBM now
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ALE0 <= 0;
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end
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end
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/* Sent, ready, BERR control */
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always @(posedge CLK) begin
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if (~BACT) Sent <= 0;
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else if (BACT && IOCS && !ALE1 && !Sent && (TS==0 || IOPWCS)) Sent <= 1;
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end
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always @(posedge CLK) begin
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if (~BACT) begin
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// Deassert IOReady and /BERR when bus inactive
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IOReady <= 0;
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nBERR_FSB <= 1;
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end else if (BACT && IOCS && !IOPWCS && !ALE1 && Sent &&
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(TS==0 || (TS==1 && !IOACTr))) begin
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// If transaction submitted, FIFO second level empty,
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// and in or entering TS0, all transactions including
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// current are complete. So terminate cycle.
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IOReady <= !IOBERR;
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nBERR_FSB <= !IOBERR;
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end
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end
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assign IOBS_Ready = !IOCS || ((IOReady) || (IOPWCS && !ALE1));
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endmodule
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