83 lines
2.1 KiB
Verilog
83 lines
2.1 KiB
Verilog
module CNT(
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/* FSB clock and E clock inputs */
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input CLK, input E,
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/* Refresh request */
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output reg RefReq, output reg RefUrg,
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/* Reset, button */
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output reg nRESout, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output reg nBR_IOB);
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/* E clock synchronization */
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reg [1:0] Er;
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wire EFall = Er[1] && !Er[0];
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always @(posedge CLK) Er[1:0] <= { Er[0], E };
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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* Refresh timer sequence
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* | Timer | RefReq | RefUrg |
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* |---------|--------|-----------|
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* | 0 0000 | 0 | 0 |
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* | 1 0001 | 1 | 0 |
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* | 2 0010 | 1 | 0 |
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* | 3 0011 | 1 | 0 |
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* | 4 0100 | 1 | 0 |
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* | 5 0101 | 1 | 0 |
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* | 6 0110 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 8 1000 | 1 | 0 |
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* | 9 1001 | 1 | 0 |
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* | 10 1010 | 1 | 1 |
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* back to timer==0
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*/
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reg [3:0] Timer = 0;
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wire TimerTC = RefUrg;
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always @(posedge CLK) begin
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if (EFall) begin
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if (TimerTC) Timer <= 0;
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else Timer <= Timer+1;
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RefUrg <= Timer==9;
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RefReq <= !(Timer==10);
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end
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end
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/* Long timer counts from 0 to 8191 -- 8192 states == 115.033 ms */
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reg [12:0] LTimer;
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reg LTimerTC;
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always @(posedge CLK) begin
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if (EFall && TimerTC) begin
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LTimer <= LTimer+1;
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LTimerTC <= LTimer[12:0]==13'h1FFE;
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end
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end
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reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
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/* Startup sequence control */
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reg [1:0] INITS = 0;
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wire INITSTC = EFall && TimerTC && LTimerTC;
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always @(posedge CLK) begin
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case (INITS[1:0])
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2'h0: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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if (INITSTC) INITS <= 1;
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end 2'h1: begin
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AoutOE <= 0;
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nRESout <= 0;
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nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
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if (INITSTC && nIPL2r) INITS <= 2;
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end 2'h2: begin
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AoutOE <= !nBR_IOB;
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nRESout <= 0;
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if (INITSTC) INITS <= 3;
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end 2'h3: begin
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nRESout <= 1; // Release reset
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INITS <= 3;
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end
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endcase
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end
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endmodule
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