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14 lines
226 B
Verilog
14 lines
226 B
Verilog
module CLK(
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input CLK, output reg [2:0] SS,
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output reg MCLK, output RCLK);
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always @(posedge CLK) begin
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SS[1:0] <= SS[1:0]+1;
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end
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always @(posedge CLK) begin
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MCLK <= SS[1:0]==2'b01 || SS[1:0]==2'b10;
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end
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endmodule
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