89 lines
2.5 KiB
Verilog
89 lines
2.5 KiB
Verilog
module CNT(
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/* C8M clock input */
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input C8M, input E, input Er,
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/* Refresh request */
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output reg RefReq, output RefUrgent,
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/* Reset, switch, button */
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input [3:1] SW, output reg nRESout, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output reg nBR_IOB,
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/* Configuration outputs */
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output C20MEN, output C25MEN, output FastROMEN);
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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* Refresh timer sequence
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* | Timer | RefReq | RefUrgent |
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* |------------------------------|
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* | 0 0000 | 0 | 0 |
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* | 1 0001 | 0 | 0 |
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* | 2 0010 | 0 | 0 |
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* | 3 0011 | 1 | 0 |
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* | 4 0100 | 1 | 0 |
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* | 5 0101 | 1 | 0 |
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* | 6 0110 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 8 1000 | 1 | 1 |
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* | 9 1001 | 1 | 1 |
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* | 10 1010 | 1 | 1 |
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* back to timer==0
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*/
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reg [3:0] Timer = 0;
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reg TimerTC;
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assign RefUrgent = Timer[3];
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always @(negedge C8M) begin
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if (Er && !E) begin
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TimerTC <= Timer[3:0]==4'h8;
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if (TimerTC) Timer <= 0;
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else Timer <= Timer+1;
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RefReq <= Timer[3:0]==4'h2 ||
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Timer[3:0]==4'h3 || Timer[3:0]==4'h4 || Timer[3:0]==4'h5 ||
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Timer[3:0]==4'h6 || Timer[3:0]==4'h7 || Timer[3:0]==4'h8;
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end
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end
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/* Long timer counts from 0 to 8192 -- 8193 states == 115.046 ms */
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reg [13:0] LTimer;
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wire LTimerTC = LTimer[13];
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always @(negedge C8M) begin
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if (Er && !E) && TimerTC begin
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if (LTimerTC) LTimer <= 0;
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else LTimer <= LTimer+1;
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end
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end
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/* Startup sequence control */
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reg [1:0] INITS = 0;
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assign nAoutOE = !AoutOE;
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always @(negedge C8M) begin
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case (INITS)
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0: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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if (LTimerTC) INITS <= 1;
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else INITS <= 0;
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end 1: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= nBR_IOB | !nIPL2; // Disable bus request if NMI pressed
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if (LTimerTC && !IPL2r) INITS <= 2;
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end 2: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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if (LTimerTC) INITS <= 3;
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end 3: begin
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AoutOE <= !nBR_IOB; // Get on PDS bus if bus was requested
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nRESout <= 1; // Release reset
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INITS <= 3;
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end
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endcase
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1;
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assign C25MEN = 1;
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// Enable fast ROM
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assign FastROMEN = 1;
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endmodule
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