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251 lines
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251 lines
13 KiB
HTML
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<!--(Document created with RoboEditor. )============================-->
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<title>CPLD Timing Analysis Glossary</title>
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<meta http-equiv=Content-Type content="text/html; charset=UTF-8">
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<meta name=Author content=administrator>
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<meta name=date content="04 8, 2003 10:49:54 AM">
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<link rel=StyleSheet href=xilhtml.css>
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</head>
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<!--(Body)==========================================================-->
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<body>
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<h1>Introduction</h1>
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<p>This report is the result of a static timing analysis of your design
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after it has been fit in the device that you selected. The timing values
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given represent the worst-case values over the recommended operating conditions
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for the part. </p>
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<h1>Overview</h1>
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<p>The timing report consists of a series of sections: </p>
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<h2>Summary</h2>
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<p>This table summarizes the external timing parameters for your device,
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including <a href="#tPD"><!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}--></a>,
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<a href="#tCO"><!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--></a>,
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<a href="#tSU"><!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--></a>,
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<a href="#tCYC"><!--kadov_tag{{<ignored>}}-->tCYC<!--kadov_tag{{</ignored>}}--></a>,
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and <a href="#fSYSTEM"><!--kadov_tag{{<ignored>}}-->fSYSTEM<!--kadov_tag{{</ignored>}}--></a>.
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<!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->For a more
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detailed description of the timing model for your device, please refer
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to the application notes linked below.</p>
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<h2>Timing Constraints</h2>
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<p>This section reports on any timing constraints that you created for
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your design. Timing constraints can be entered using the Constraints Editor
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tool, or by editing an Implementation Constraints File directly. For more
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information on creating timing constraints, see the Constraints Guide.
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</p>
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<p class=Note><span style="font-weight: bold;">Note</span> that if you
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did not define any constraints for your design, then the timing analysis
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software will automatically create a default set of constraints for you.
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These include pad-to-pad, register-to-register, pad-to-register, and period
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constraints. A constraint value of 0 <!--kadov_tag{{<ignored>}}-->ns<!--kadov_tag{{</ignored>}}-->
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will be used for all of these automatically generated constraints. As
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a result, all paths listed under each constraint will violate the constraint,
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and will have a negative value for slack.</p>
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<p class=Note><span style="font-weight: bold;">Note</span> also that to
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limit the size of the report, each path endpoint involved in a timing
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path will only be listed once, under a single constraint. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}--></p>
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<p>For each timing path listed under a constraint, there is a hyperlink
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that can be used to open a window listing the individual internal delay
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elements traversed in the path. To understand these delay elements, consult
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the <a href="#Definitions">Definitions</a> section below, or the following
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application notes and white papers: </p>
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<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP375: Understanding
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the <!--kadov_tag{{<ignored>}}-->CoolRunner-II<!--kadov_tag{{</ignored>}}-->
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Timing Model</a> </p>
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<p><a href="http://www.xilinx.com/publications/whitepapers/index.htm">WP122:
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Using the <!--kadov_tag{{<ignored>}}-->CoolRunner<!--kadov_tag{{</ignored>}}-->
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XPLA3 Timing Model</a> </p>
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<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP071: Using
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the XC9500 Timing Model</a> </p>
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<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP111: Using
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the XC9500XL Timing Model</a></p>
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<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2"><!--kadov_tag{{<ignored>}}-->XAPP<!--kadov_tag{{</ignored>}}-->
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362: Using the XC9500XV Timing Model</a></p>
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<p>available in the literature section of <a href="http://www.xilinx.com"><!--kadov_tag{{<ignored>}}-->www.xilinx.com</a>.<!--kadov_tag{{</ignored>}}-->
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</p>
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<h2>Data Sheet Report</h2>
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<p>This section of the report lists the external timing parameters for
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your design. This includes; maximum external clock speed for each clock,
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setup and hold times for each registered input, clock-to-output pad timing
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for each registered output, clock to setup time for each register-to-register
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timing path, and pad-to-pad time for each combinatorial path through your
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design. </p>
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<h2>Going Further</h2>
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<p>To do more advanced timing analysis of your design, select the process
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<span style="font-weight: bold;">Analyze Post-Fit Static Timing</span>
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in <!--kadov_tag{{<ignored>}}-->iSE<!--kadov_tag{{</ignored>}}-->. This
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will run <!--kadov_tag{{<ignored>}}-->Xilinx's<!--kadov_tag{{</ignored>}}-->
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Timing Analyzer tool interactively. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->The
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Timing Analyzer provides a powerful, flexible, and easy way to perform
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static timing analysis on <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}-->
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and <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> designs.
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With Timing Analyzer, analysis can be performed immediately after mapping,
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placing or routing an <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}-->
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design, and after fitting and routing a <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}-->
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design. </p>
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<p>Timing Analyzer verifies that the delay along a given path or paths
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meets specified timing requirements. It organizes and displays data that
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allows you to analyze critical paths in a circuit, the cycle time of the
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circuit, the delay along any specified <!--kadov_tag{{<ignored>}}-->path(s<!--kadov_tag{{</ignored>}}-->),
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and the path with the greatest delay. It also provides a quick analysis
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of the effect different speed grades have on the same design. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}--></p>
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<p>Timing Analyzer performs setup and hold checks (skew analysis). It works
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with synchronous systems composed of synchronous elements and combinatorial
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logic. In synchronous design, Timing Analyzer takes into account all path
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delays, including clock-to-out and setup requirements, while calculating
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the worst-case timing of the design. </p>
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<p>Timing Analyzer creates timing analysis reports based on existing timing
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constraints or user specified paths within the program. Timing reports
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have a hierarchical browser to quickly jump to different sections of the
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reports. Timing paths in reports can be cross probed to synthesis tools
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(Exemplar and <!--kadov_tag{{<ignored>}}-->Synplicity<!--kadov_tag{{</ignored>}}-->)
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and <!--kadov_tag{{<ignored>}}-->Floorplanner<!--kadov_tag{{</ignored>}}-->.
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</p>
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<p>There are several ways to issue commands in Timing Analyzer. Timing
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Analyzer can be controlled through <!--kadov_tag{{<ignored>}}-->GUI<!--kadov_tag{{</ignored>}}-->
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features (menu commands) or its comprehensive macro command language facility.
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You can select from menus, click toolbar buttons, type keyboard commands
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in the console window, and run macros. </p>
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<h1><a name=Definitions></a>Definitions</h1>
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<h2><a name=tPD></a>Pad to Pad (<!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}-->)
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</h2>
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<p>Reports pad to pad paths that start at input pads and end at output
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pads. The maximum external pad to pad delay. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->Combinatorial
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pad-to-pad paths begin at input pads, propagate through one or more levels
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of combinatorial logic and end at output pads. Combinatorial paths also
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trace through the enable inputs of 3-state controlled pads. Combinatorial
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paths are not traced through clock, and asynchronous set and reset inputs
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of registers. These paths are also broken at bidirectional pins</p>
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<h2><a name=tCO></a>Clock Pad to Output Pad (<!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->)
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</h2>
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<p>The maximum external clock pad to output pad delay. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->Reports
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paths that start at input <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->pads
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trace through clock inputs of <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->registers
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and end at output pads. Paths are not traced through PRE/<!--kadov_tag{{<ignored>}}-->CLR<!--kadov_tag{{</ignored>}}-->
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<!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->inputs
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of registers. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->You
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can directly specify <!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->
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for all registered output paths in your design using the Pad-to-Pad <!--kadov_tag{{<ignored>}}-->timespec<!--kadov_tag{{</ignored>}}-->.
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Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate
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through global clock buffers, and propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}-->
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output and any number of levels of combinatorial logic and end at the
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output pad. Clock-Pad-to-Pad paths for product term clock paths begin
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at input pads, propagate through any number of logic levels feeding into
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a clock product term, propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}-->
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output and any number of levels of combinatorial logic and end at the
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output pad. Clock-Pad-to-Pad paths also trace through the enable inputs
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of 3-state controlled pads.</p>
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<h2><a name=tSU></a>Setup to Clock at Pad (<!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->
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or <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) </h2>
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<p>Reports external setup time of data <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->to
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clock at pad. Data path starts at an input pad and ends at register <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->(Fast
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Input Register for <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->)
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D/<!--kadov_tag{{<ignored>}}-->T<!--kadov_tag{{</ignored>}}--> <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->input.
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Clock path starts at input pad and ends at the register clock input. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->Paths
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are not traced through registers. Pin-to-pin setup requirement is not
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reported or guaranteed for product-term clocks derived from <!--kadov_tag{{<ignored>}}-->macrocell<!--kadov_tag{{</ignored>}}-->
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feedback signals. </p>
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<p>The minimum required setup time for flip-flops. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->You
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can specify the <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->
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(setup-to-clock) for all inputs in your design relative to a global clock
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or product term clock. Each <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->
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OFFSET timespec involves an input path and a clock path. Input paths start
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at input pads, propagate through input buffers and any number of combinatorial
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logic levels before ending at a flip-flop D/T input, including the receiving
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flip-flop's tSU. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->Input
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paths are not traced through flip-flop clock pins, asynchronous set/reset
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inputs or bidirectional I/O pins. Global clock paths start at global clock
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pads, propagate through global clock buffers and end at the flip-flop
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clock pin. Product term clock paths start at input pads, propagate through
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a single level of logic implemented in a clock product term and end at
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the flip-flop clock pin.</p>
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<h2><a name=tCYC></a>Clock to Setup (tCYC) </h2>
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<p>Register to register cycle time. Includes source register tCO and destination
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register tSU. </p>
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<p class=Note><span style="font-weight: bold;">Note</span> that when the
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computed Maximum Clock Speed is limited by tCYC, it is computed assuming
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that all registers are rising-edge sensitive. </p>
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<h2><a name=fSYSTEM></a>fSYSTEM </h2>
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<p>Maximum clock operating frequency. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->You
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can specify the fSYSTEM (clock frequency or period) for all registered
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paths in your design using a Register-to-Register timespec. Register-to-Register
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paths begin at flip-flop clock inputs, propagate through the flip-flop
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Q output and any number of levels of combinatorial logic and end at the
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receiving flip-flop D/T input, including the receiving flip-flop's tSU.
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When these flip-flops are clocked by the same clock, the delay on this
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path is equivalent to the cycle time of the clock. Registered paths do
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not propagate through clock, and asynchronous set and reset inputs of
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registers as shown below. These paths are also broken at bidirectional
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pins.</p>
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<p> </p>
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</body>
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</html>
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