42 lines
3.4 KiB
XML
42 lines
3.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!-- IMPORTANT: This is an internal file that has been generated
|
|
by the Xilinx ISE software. Any direct editing or
|
|
changes made to this file may result in unpredictable
|
|
behavior or data corruption. It is strongly advised that
|
|
users do not edit the contents of this file. -->
|
|
<messages>
|
|
<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of '<arg fmt="%s" index="1">WarpSE.ise</arg>'.
|
|
</msg>
|
|
|
|
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">C16M</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P22</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
|
|
</msg>
|
|
|
|
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">C8M</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P23</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
|
|
</msg>
|
|
|
|
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">FCLK</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P27</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">C20MEN</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">SW<1></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">SW<2></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">SW<3></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">nBG_IOB</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="error" file="Cpld" num="892" delta="new" >Cannot place signal <arg fmt="%s" index="1">iobm/IOS_FSM_FFd4</arg>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions.
|
|
</msg>
|
|
|
|
<msg type="error" file="Cpld" num="868" delta="new" >Cannot fit the design into any of the specified devices with the selected implementation options.
|
|
</msg>
|
|
|
|
</messages>
|