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Warp-SE/cpld/XC95144XL/WarpSE.syr
Zane Kaminski 85d1d103b7 Better CPLD stuff
2022-03-29 04:23:54 -04:00

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Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.84 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.87 secs
--> Reading design: WarpSE.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "WarpSE.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "WarpSE"
Output Format : NGC
Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : WarpSE
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../RAM.v" in library work
Compiling verilog file "../IOBS.v" in library work
Module <RAM> compiled
Compiling verilog file "../IOBM.v" in library work
Module <IOBS> compiled
Compiling verilog file "../FSB.v" in library work
Module <IOBM> compiled
Compiling verilog file "../CS.v" in library work
Module <FSB> compiled
Compiling verilog file "../CNT.v" in library work
Module <CS> compiled
Compiling verilog file "../WarpSE.v" in library work
Module <CNT> compiled
Module <WarpSE> compiled
No errors in compilation
Analysis of file <"WarpSE.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <WarpSE> in library <work>.
Analyzing hierarchy for module <CS> in library <work>.
Analyzing hierarchy for module <RAM> in library <work>.
Analyzing hierarchy for module <IOBS> in library <work>.
Analyzing hierarchy for module <IOBM> in library <work>.
Analyzing hierarchy for module <CNT> in library <work>.
Analyzing hierarchy for module <FSB> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <WarpSE>.
Module <WarpSE> is correct for synthesis.
Analyzing module <CS> in library <work>.
Module <CS> is correct for synthesis.
Analyzing module <RAM> in library <work>.
Module <RAM> is correct for synthesis.
Analyzing module <IOBS> in library <work>.
Module <IOBS> is correct for synthesis.
Analyzing module <IOBM> in library <work>.
Module <IOBM> is correct for synthesis.
Analyzing module <CNT> in library <work>.
Module <CNT> is correct for synthesis.
Analyzing module <FSB> in library <work>.
Module <FSB> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <CS>.
Related source file is "../CS.v".
Found 1-bit register for signal <nOverlay0>.
Found 1-bit register for signal <nOverlay1>.
Summary:
inferred 2 D-type flip-flop(s).
Unit <CS> synthesized.
Synthesizing Unit <RAM>.
Related source file is "../RAM.v".
Found finite state machine <FSM_0> for signal <RS>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 18 |
| Inputs | 6 |
| Outputs | 9 |
| Clock | CLK (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <nCAS>.
Found 1-bit register for signal <BACTr>.
Found 1-bit register for signal <Once>.
Found 1-bit register for signal <RAMDIS1>.
Found 1-bit register for signal <RAMDIS2>.
Found 1-bit register for signal <RAMReady>.
Found 1-bit register for signal <RASEL>.
Found 1-bit register for signal <RefRAS>.
Summary:
inferred 1 Finite State Machine(s).
inferred 6 D-type flip-flop(s).
Unit <RAM> synthesized.
Synthesizing Unit <IOBS>.
Related source file is "../IOBS.v".
Found finite state machine <FSM_1> for signal <PS>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 5 |
| Outputs | 5 |
| Clock | CLK (rising_edge) |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <BERR>.
Found 1-bit register for signal <IOREQ>.
Found 1-bit register for signal <IORW0>.
Found 1-bit register for signal <IOL0>.
Found 1-bit register for signal <IOU0>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <ALE1>.
Found 1-bit register for signal <Clear1>.
Found 1-bit register for signal <IOACTr>.
Found 1-bit register for signal <IOL1>.
Found 1-bit register for signal <IOReady>.
Found 1-bit register for signal <IORW1>.
Found 1-bit register for signal <IOU1>.
Found 1-bit register for signal <Load1>.
Found 1-bit register for signal <Once>.
Summary:
inferred 1 Finite State Machine(s).
inferred 9 D-type flip-flop(s).
Unit <IOBS> synthesized.
Synthesizing Unit <IOBM>.
Related source file is "../IOBM.v".
Found finite state machine <FSM_2> for signal <IOS>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 16 |
| Inputs | 7 |
| Outputs | 8 |
| Clock | C16M (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <IOBERR>.
Found 1-bit register for signal <nASout>.
Found 1-bit register for signal <IOACT>.
Found 1-bit register for signal <nLDS>.
Found 1-bit register for signal <nUDS>.
Found 1-bit register for signal <nDinLE>.
Found 1-bit register for signal <nDoutOE>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <nVMA>.
Found 1-bit register for signal <BERRrf>.
Found 1-bit register for signal <BERRrr>.
Found 1-bit register for signal <BG>.
Found 1-bit register for signal <BGr0>.
Found 1-bit register for signal <BGr1>.
Found 1-bit register for signal <DTACKrf>.
Found 1-bit register for signal <DTACKrr>.
Found 1-bit register for signal <Er>.
Found 1-bit register for signal <Er2>.
Found 5-bit up counter for signal <ES>.
Found 1-bit register for signal <ETACK>.
Found 1-bit register for signal <IOREQr>.
Found 1-bit register for signal <RESrf>.
Found 1-bit register for signal <RESrr>.
Found 1-bit register for signal <VPArf>.
Found 1-bit register for signal <VPArr>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 22 D-type flip-flop(s).
Unit <IOBM> synthesized.
Synthesizing Unit <CNT>.
Related source file is "../CNT.v".
Found 1-bit register for signal <TimeoutA>.
Found 1-bit register for signal <TimeoutB>.
Found 8-bit up counter for signal <RefCnt>.
Found 1-bit register for signal <RefDone>.
Found 1-bit register for signal <TimeoutBPre>.
Summary:
inferred 1 Counter(s).
Unit <CNT> synthesized.
Synthesizing Unit <FSB>.
Related source file is "../FSB.v".
Found 1-bit register for signal <nDTACK>.
Found 1-bit register for signal <ASrf>.
Found 1-bit register for signal <BERR0r>.
Found 1-bit register for signal <BERR1r>.
Found 1-bit register for signal <Ready0r>.
Found 1-bit register for signal <Ready1r>.
Found 1-bit register for signal <Ready2r>.
Found 1-bit register for signal <VPA>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <FSB> synthesized.
Synthesizing Unit <WarpSE>.
Related source file is "../WarpSE.v".
WARNING:Xst:647 - Input <SW<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit tristate buffer for signal <nAS_IOB>.
Found 1-bit tristate buffer for signal <nLDS_IOB>.
Found 1-bit tristate buffer for signal <nUDS_IOB>.
Found 1-bit tristate buffer for signal <nVMA_IOB>.
Found 1-bit register for signal <Disable>.
Found 1-bit register for signal <IPL2r0>.
Found 1-bit register for signal <IPL2r1>.
Found 1-bit register for signal <RESDone>.
Found 1-bit register for signal <RESr0>.
Found 1-bit register for signal <RESr1>.
Found 1-bit register for signal <RESr2>.
Summary:
inferred 7 D-type flip-flop(s).
inferred 4 Tristate(s).
Unit <WarpSE> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 2
5-bit up counter : 1
8-bit up counter : 1
# Registers : 68
1-bit register : 68
# Tristates : 4
1-bit tristate buffer : 4
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:3]> with gray encoding.
-------------------
State | Encoding
-------------------
000 | 000
001 | 001
010 | 011
011 | 010
100 | 110
101 | 111
110 | 101
111 | 100
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <iobs/PS/FSM> on signal <PS[1:2]> with johnson encoding.
-------------------
State | Encoding
-------------------
00 | 00
11 | 01
10 | 11
01 | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <ram/RS/FSM> on signal <RS[1:3]> with compact encoding.
-------------------
State | Encoding
-------------------
000 | 000
010 | 010
101 | 001
001 | 101
011 | 011
100 | 111
111 | 100
110 | 110
-------------------
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable.
You should achieve better results by setting this init to 1.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 3
# Counters : 2
5-bit up counter : 1
8-bit up counter : 1
# Registers : 47
Flip-Flops : 47
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE.
You should achieve better results by setting this init to 1.
Optimizing unit <WarpSE> ...
implementation constraint: INIT=r : RESr0
implementation constraint: INIT=r : RESr1
implementation constraint: INIT=r : RESr2
implementation constraint: INIT=r : IPL2r0
implementation constraint: INIT=r : IPL2r1
implementation constraint: INIT=r : Disable
implementation constraint: INIT=r : RESDone
implementation constraint: INIT=r : ram/RAMReady
implementation constraint: INIT=r : ram/RASEL
implementation constraint: INIT=r : ram/RAMDIS1
implementation constraint: INIT=r : ram/RefRAS
implementation constraint: INIT=r : ram/RAMDIS2
implementation constraint: INIT=r : ram/Once
implementation constraint: INIT=r : iobs/IOACTr
implementation constraint: INIT=r : ram/RS_FSM_FFd1
implementation constraint: INIT=r : iobs/Once
implementation constraint: INIT=r : cs/nOverlay0
implementation constraint: INIT=r : cs/nOverlay1
implementation constraint: INIT=r : iobs/PS_FSM_FFd1
implementation constraint: INIT=r : iobs/PS_FSM_FFd2
implementation constraint: INIT=r : iobm/ETACK
implementation constraint: INIT=r : iobm/BGr0
implementation constraint: INIT=r : iobm/BGr1
implementation constraint: INIT=r : iobm/BG
implementation constraint: INIT=r : iobm/IOREQr
implementation constraint: INIT=r : fsb/ASrf
implementation constraint: INIT=r : ram/RS_FSM_FFd2
implementation constraint: INIT=r : cnt/RefDone
implementation constraint: INIT=r : cnt/RefCnt_0
implementation constraint: INIT=r : cnt/RefCnt_1
implementation constraint: INIT=r : cnt/RefCnt_2
implementation constraint: INIT=r : cnt/RefCnt_3
implementation constraint: INIT=r : cnt/RefCnt_4
implementation constraint: INIT=r : cnt/RefCnt_5
implementation constraint: INIT=r : cnt/RefCnt_6
implementation constraint: INIT=r : cnt/RefCnt_7
implementation constraint: INIT=r : ram/RS_FSM_FFd3
implementation constraint: INIT=r : iobm/IOS_FSM_FFd1
implementation constraint: INIT=r : iobm/IOS_FSM_FFd2
implementation constraint: INIT=r : iobm/IOS_FSM_FFd3
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : WarpSE.ngr
Top Level Output File Name : WarpSE
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 75
Cell Usage :
# BELS : 596
# AND2 : 165
# AND3 : 25
# AND4 : 15
# AND5 : 3
# AND6 : 1
# AND7 : 1
# AND8 : 3
# GND : 1
# INV : 265
# OR2 : 98
# OR3 : 5
# OR4 : 1
# VCC : 1
# XOR2 : 12
# FlipFlops/Latches : 89
# FD : 60
# FDCE : 29
# Tri-States : 1
# BUFE : 1
# IO Buffers : 74
# IBUF : 39
# OBUF : 31
# OBUFE : 4
=========================================================================
Total REAL time to Xst completion: 39.00 secs
Total CPU time to Xst completion: 38.76 secs
-->
Total memory usage is 236884 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 5 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
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