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18 lines
1.1 KiB
Plaintext
18 lines
1.1 KiB
Plaintext
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'MXSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK2X_IOB' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_FSB' based upon the LOC
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constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_IOB' based upon the LOC
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constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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