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622efc7916
Warp-SE/cpld/XC95144XL/WarpSE.syr
Zane Kaminski 622efc7916 0.7c-slow compiled and working
2024-10-15 03:41:01 -04:00

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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
--> Reading design: WarpSE.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "WarpSE.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "WarpSE"
Output Format : NGC
Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : WarpSE
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../RAM.v" in library work
Compiling verilog file "../IOBS.v" in library work
Module <RAM> compiled
Compiling verilog file "../IOBM.v" in library work
Module <IOBS> compiled
Compiling verilog file "../FSB.v" in library work
Module <IOBM> compiled
Compiling verilog file "../CS.v" in library work
Module <FSB> compiled
Compiling verilog file "../CNT.v" in library work
Module <CS> compiled
Compiling verilog file "../WarpSE.v" in library work
Module <CNT> compiled
Module <WarpSE> compiled
No errors in compilation
Analysis of file <"WarpSE.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <WarpSE> in library <work>.
Analyzing hierarchy for module <CS> in library <work>.
Analyzing hierarchy for module <RAM> in library <work>.
Analyzing hierarchy for module <IOBS> in library <work>.
Analyzing hierarchy for module <IOBM> in library <work>.
Analyzing hierarchy for module <CNT> in library <work>.
Analyzing hierarchy for module <FSB> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <WarpSE>.
Module <WarpSE> is correct for synthesis.
Analyzing module <CS> in library <work>.
Module <CS> is correct for synthesis.
Analyzing module <RAM> in library <work>.
Module <RAM> is correct for synthesis.
Analyzing module <IOBS> in library <work>.
Module <IOBS> is correct for synthesis.
Analyzing module <IOBM> in library <work>.
Module <IOBM> is correct for synthesis.
Analyzing module <CNT> in library <work>.
Module <CNT> is correct for synthesis.
Analyzing module <FSB> in library <work>.
Module <FSB> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <QoSEN> in unit <CNT> has a constant value of 1 during circuit operation. The register is replaced by logic.
Synthesizing Unit <CS>.
Related source file is "../CS.v".
WARNING:Xst:647 - Input <A<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <Overlay>.
Unit <CS> synthesized.
Synthesizing Unit <RAM>.
Related source file is "../RAM.v".
Found 8x3-bit ROM for signal <RS$rom0000>.
Found 1-bit register for signal <nCAS>.
Found 1-bit register for signal <nOE>.
Found 1-bit register for signal <CASEndEN>.
Found 1-bit register for signal <RAMReadyReg>.
Found 1-bit register for signal <RASEL>.
Found 1-bit register for signal <RASEN>.
Found 1-bit register for signal <RASrf>.
Found 1-bit register for signal <RefCAS>.
Found 1-bit register for signal <RefDone>.
Found 3-bit register for signal <RS>.
Summary:
inferred 1 ROM(s).
inferred 8 D-type flip-flop(s).
Unit <RAM> synthesized.
Synthesizing Unit <IOBS>.
Related source file is "../IOBS.v".
Found finite state machine <FSM_0> for signal <TS>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 5 |
| Outputs | 5 |
| Clock | CLK (rising_edge) |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <IORW>.
Found 1-bit register for signal <IOREQ>.
Found 1-bit register for signal <IOL0>.
Found 1-bit register for signal <IONPReady>.
Found 1-bit register for signal <IOU0>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <ALE1>.
Found 1-bit register for signal <nBERR_FSB>.
Found 1-bit register for signal <Clear1>.
Found 1-bit register for signal <IOACTr>.
Found 2-bit register for signal <IODONEr>.
Found 1-bit register for signal <IODONErf>.
Found 1-bit register for signal <IOL1>.
Found 1-bit register for signal <IORW1>.
Found 1-bit register for signal <IOU1>.
Found 1-bit register for signal <Load1>.
Found 1-bit register for signal <Sent>.
Summary:
inferred 1 Finite State Machine(s).
inferred 10 D-type flip-flop(s).
Unit <IOBS> synthesized.
Synthesizing Unit <IOBM>.
Related source file is "../IOBM.v".
WARNING:Xst:646 - Signal <IOS0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found finite state machine <FSM_1> for signal <IOS>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 12 |
| Inputs | 4 |
| Outputs | 7 |
| Clock | C16M (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <RnW>.
Found 1-bit register for signal <IOACT>.
Found 1-bit register for signal <nAS>.
Found 1-bit register for signal <nLDS>.
Found 1-bit register for signal <nUDS>.
Found 1-bit register for signal <nDinLE>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <nVMA>.
Found 1-bit register for signal <C8Mr>.
Found 1-bit register for signal <DoutOE>.
Found 1-bit register for signal <Er>.
Found 4-bit up counter for signal <ES>.
Found 1-bit register for signal <IODONEr>.
Found 1-bit register for signal <IOREQr>.
Found 1-bit register for signal <VPAr>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 13 D-type flip-flop(s).
Unit <IOBM> synthesized.
Synthesizing Unit <CNT>.
Related source file is "../CNT.v".
WARNING:Xst:646 - Signal <nRESr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <VIACSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SndCSWRr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SCSICSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SCCCSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IWMCSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IACK1CSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IACK0CSr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit register for signal <RefUrg>.
Found 1-bit register for signal <RefReq>.
Found 1-bit register for signal <nBR_IOB>.
Found 1-bit register for signal <nPOR>.
Found 1-bit register for signal <nRESout>.
Found 1-bit register for signal <AoutOE>.
Found 1-bit register for signal <MCKE>.
Found 4-bit register for signal <C8Mr>.
Found 2-bit register for signal <Er>.
Found 2-bit register for signal <IS>.
Found 12-bit up counter for signal <LTimer>.
Found 1-bit register for signal <LTimerTick>.
Found 4-bit up counter for signal <Timer>.
Found 1-bit register for signal <TimerTick>.
Summary:
inferred 2 Counter(s).
inferred 8 D-type flip-flop(s).
Unit <CNT> synthesized.
Synthesizing Unit <FSB>.
Related source file is "../FSB.v".
Found 1-bit register for signal <nVPA>.
Found 1-bit register for signal <BACTr>.
Found 1-bit register for signal <nDTACK>.
Found 1-bit register for signal <ASrf>.
Summary:
inferred 4 D-type flip-flop(s).
Unit <FSB> synthesized.
Synthesizing Unit <WarpSE>.
Related source file is "../WarpSE.v".
WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DBG> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <nPOR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit tristate buffer for signal <RnW_IOB>.
Found 1-bit tristate buffer for signal <nAS_IOB>.
Found 1-bit tristate buffer for signal <nBR_IOB>.
Found 1-bit tristate buffer for signal <nLDS_IOB>.
Found 1-bit tristate buffer for signal <nRES>.
Found 1-bit tristate buffer for signal <nUDS_IOB>.
Found 1-bit tristate buffer for signal <nVMA_IOB>.
Summary:
inferred 7 Tristate(s).
Unit <WarpSE> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 1
8x3-bit ROM : 1
# Counters : 3
12-bit up counter : 1
4-bit up counter : 2
# Registers : 59
1-bit register : 55
2-bit register : 2
3-bit register : 1
4-bit register : 1
# Tristates : 7
1-bit tristate buffer : 7
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:7]> with one-hot encoding.
-------------------
State | Encoding
-------------------
000 | 0000001
010 | 0000010
011 | 0000100
100 | 0001000
101 | 0010000
110 | 0100000
111 | 1000000
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
-------------------
State | Encoding
-------------------
00 | 00
11 | 01
10 | 11
01 | 10
-------------------
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <0> is unconnected in block <RAMReadyReg>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# ROMs : 1
8x3-bit ROM : 1
# Counters : 3
12-bit up counter : 1
4-bit up counter : 2
# Registers : 43
Flip-Flops : 43
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <WarpSE> ...
Optimizing unit <CS> ...
Optimizing unit <FSB> ...
Optimizing unit <RAM> ...
Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd1
Optimizing unit <IOBM> ...
implementation constraint: INIT=s : IOS_FSM_FFd7
implementation constraint: INIT=r : DoutOE
implementation constraint: INIT=r : IOS_FSM_FFd5
implementation constraint: INIT=r : IOS_FSM_FFd6
implementation constraint: INIT=r : IOS_FSM_FFd1
implementation constraint: INIT=r : IOS_FSM_FFd2
implementation constraint: INIT=r : IOS_FSM_FFd3
implementation constraint: INIT=r : IOS_FSM_FFd4
Optimizing unit <CNT> ...
implementation constraint: INIT=r : IS_0
implementation constraint: INIT=r : IS_1
implementation constraint: INIT=r : Timer_3
implementation constraint: INIT=r : Timer_0
implementation constraint: INIT=r : Timer_1
implementation constraint: INIT=r : Timer_2
WARNING:Xst:2677 - Node <RAMReadyReg> of sequential type is unconnected in block <ram>.
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : WarpSE.ngr
Top Level Output File Name : WarpSE
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 80
Cell Usage :
# BELS : 539
# AND2 : 168
# AND3 : 21
# AND4 : 8
# AND5 : 3
# AND8 : 1
# GND : 7
# INV : 215
# OR2 : 85
# OR3 : 8
# OR4 : 4
# OR5 : 1
# XOR2 : 18
# FlipFlops/Latches : 94
# FD : 58
# FDCE : 31
# FDCP : 1
# FDP : 2
# FDPE : 2
# IO Buffers : 73
# IBUF : 35
# IOBUFE : 1
# OBUF : 31
# OBUFE : 6
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.96 secs
-->
Total memory usage is 260640 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 15 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
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