32 lines
718 B
Verilog
32 lines
718 B
Verilog
module CNT(
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/* FSB clock and AS detection */
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input FCLK, input CACT,
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/* Refresh request */
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output RefReq, output RefUrgent, input RefAck,
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/* Timeout signals */
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output reg TimeoutA, output reg TimeoutB);
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/* Refresh counter */
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reg [7:0] RefCnt = 0;
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reg RefDone = 0;
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assign RefReq = ~RefDone;
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assign RefUrgent = RefCnt[7] && RefCnt[6] && RefCnt[5] && ~RefDone;
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always @(posedge FCLK) begin
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RefCnt <= RefCnt+1;
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if (RefCnt==0) RefDone <= 0;
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else if (RefAck) RefDone <= 1;
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end
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/* Timeout signals */
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always @(posedge FCLK) begin
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if (~CACT) begin
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TimeoutA <= 0;
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TimeoutB <= 0;
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end else begin
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if (RefCnt==0) TimeoutA <= 1;
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if (RefCnt==0 && TimeoutA) TimeoutB <= 1;
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end
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end
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endmodule
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