124 lines
2.9 KiB
Verilog
124 lines
2.9 KiB
Verilog
module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output reg nAS, output reg nLDS, output reg nUDS, output reg nVMA,
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input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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output reg IOACT, output reg IOBERR, input IOREQ, input IOLDS, input IOUDS, input IOWE);
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/* I/O bus slave port input synchronization */
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reg IOREQr = 0;
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always @(negedge C16M) begin IOREQr <= IOREQ; end
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/* DTACK, BERR, RESET synchronization */
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reg DTACKrr, DTACKrf, VPArr, VPArf, BERRrr, BERRrf, RESrr, RESrf;
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always @(posedge C16M) begin
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DTACKrr <= ~nDTACK;
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VPArr <= ~nVPA;
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BERRrr <= ~nBERR;
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RESrr <= ~nRES;
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end
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always @(negedge C16M) begin
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DTACKrf <= ~nDTACK;
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VPArf <= ~nVPA;
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BERRrf <= ~nBERR;
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RESrf <= ~nRES;
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end
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wire DTACK = DTACKrr && DTACKrf;
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wire BERR = BERRrr && BERRrf;
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wire VPA = VPArr && VPArf;
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wire RES = RESrr && RESrf;
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/* E clock state */
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reg [4:0] ES;
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reg Er;
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reg Er2;
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always @(negedge C8M) begin Er <= E; end
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always @(posedge C16M) begin Er2 <= Er; end
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always @(posedge C16M) begin
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if (Er2 && ~Er) ES <= 1;
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else if (ES==0 || ES==19) ES <= 0;
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else ES <= ES+1;
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end
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/* ETACK and VMA generation */
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reg ETACK = 0;
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always @(posedge C16M) begin ETACK <= ES==16 && ~nVMA; end
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always @(posedge C16M) begin
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if (ES==7 && IOACT && VPA) nVMA <= 0;
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else if (ES==0) nVMA <= 1;
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end
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/* I/O bus state */
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reg [2:0] IOS = 0;
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always @(posedge C16M) begin
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if (IOS==0) begin
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if (IOREQr) begin
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if (~C8M) begin
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IOS <= 1;
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end else begin
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IOS <= 0;
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end
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IOACT <= 1;
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ALE0 <= 1;
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end else begin
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IOS <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end
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end else if (IOS==1) begin
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IOS <= 2;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==2) begin
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IOS <= 3;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==3) begin
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IOS <= 4;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==4) begin
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IOS <= 5;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==5) begin
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if (C8M && (DTACK || ETACK || BERR || RES)) begin
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IOS <= 6;
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IOACT <= 0;
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IOBERR <= ~nBERR;
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end else begin
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IOS <= 5;
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IOACT <= 1;
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end
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ALE0 <= 1;
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end else if (IOS==6) begin
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IOS <= 7;
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IOACT <= 0;
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ALE0 <= 0;
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end else if (IOS==7) begin
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IOS <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end
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end
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/* PDS address and data latch control */
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assign nAoutOE = 0;
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always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end
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always @(posedge C16M) begin
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nDoutOE <= ~(IOWE && (IOS==1 || IOS==2 || IOS==3 ||
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IOS==4 || IOS==5 || IOS==6));
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end
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/* AS, DS control */
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always @(negedge C16M) begin
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nAS <= ~(IOS==1 || IOS==2 || IOS==3 || IOS==4 || IOS==5);
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nLDS <= ~(IOLDS && (((IOS==1 || IOS==2) && ~IOWE) || IOS==3 || IOS==4 || IOS==5));
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nUDS <= ~(IOUDS && (((IOS==1 || IOS==2) && ~IOWE) || IOS==3 || IOS==4 || IOS==5));
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end
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endmodule
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