113 lines
2.3 KiB
Verilog
113 lines
2.3 KiB
Verilog
module IOBS(
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/* MC68HC000 interface */
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input CLK, input nWE, input nAS, input nLDS, input nUDS,
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/* AS cycle detection */
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input BACT,
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/* Select and ready signals */
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input IOCS, input IOPWCS, output Ready, output reg BERR,
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/* Read data OE control */
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output nDinOE,
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/* IOB Master Controller Interface */
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output reg IOREQ, input IOACT, input IOBERR,
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/* FIFO primary level control */
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output reg ALE0, output reg IORW0, output reg IOL0, output reg IOU0,
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/* FIFO secondary level control */
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output reg ALE1);
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/* IOACT input synchronization */
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reg IOACTr = 0;
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always @(posedge CLK) begin IOACTr <= IOACT; end
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/* Read data OE control */
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assign nDinOE = ~nAS && IOCS && nWE;
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/* Posted read/write state */
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reg [1:0] PS = 0;
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reg Once = 0;
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/* FIFO second level control */
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reg Load1;
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reg IORW1;
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reg IOL1;
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reg IOU1;
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always @(posedge CLK) begin
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if (PS!=0 && BACT && IOCS && ~Once && ~ALE1) begin
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ALE1 <= 1;
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IORW1 <= nWE;
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Load1 <= 1;
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end else begin
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if (PS==3) ALE1 <= 0;
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Load1 <= 0;
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end
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end
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always @(posedge CLK) begin
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if (Load1) begin
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IOL1 <= ~nLDS;
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IOU1 <= ~nUDS;
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end
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end
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/* FIFO Primary Level Control */
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always @(posedge CLK) begin
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if (PS==0) begin
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if (ALE1) begin
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PS <= 3;
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IOREQ <= 1;
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IORW0 <= IORW1;
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end else if (BACT && IOCS && ~Once) begin
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PS <= 3;
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IOREQ <= 1;
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IORW0 <= nWE;
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end else begin
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PS <= 0;
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IOREQ <= 0;
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end
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ALE0 <= 0;
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end else if (PS==3) begin
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PS <= 2;
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IOREQ <= 1;
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ALE0 <= 1;
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if (ALE1) begin
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else begin
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IOL0 <= ~nLDS;
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IOU0 <= ~nUDS;
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end
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end else if (PS==2) begin
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if (IOACTr) begin
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PS <= 1;
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IOREQ <= 0;
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end else begin
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PS <= 2;
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IOREQ <= 1;
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end
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ALE0 <= 0;
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end else if (PS==1) begin
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if (~IOACTr) PS <= 0;
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else PS <= 2;
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IOREQ <= 0;
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ALE0 <= 0;
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end
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end
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/* Once, ready, BERR control */
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reg IOReady;
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wire IOPWReady = ~ALE1;
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always @(posedge CLK) begin
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if (~BACT) Once <= 0;
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else if (IOCS && (PS==0 || (IOPWCS && IOPWReady))) Once <= 1;
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end
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always @(posedge CLK) begin
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if (~BACT) begin
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IOReady <= 0;
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BERR <= 0;
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end else if (Once && (PS==0 || PS==1) && ~IOACTr && IOPWReady) begin
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IOReady <= ~IOBERR;
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BERR <= IOBERR;
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end
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end
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assign Ready = ~IOCS || IOReady || (IOPWCS && IOPWReady);
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endmodule
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