1734 lines
88 KiB
HTML
1734 lines
88 KiB
HTML
<html><body>
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<pre>
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: MXSE Date: 10-24-2021, 6:31AM
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Device Used: XC95144XL-10-TQ100
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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106/144 ( 74%) 411 /720 ( 57%) 214/432 ( 50%) 82 /144 ( 57%) 67 /81 ( 83%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 7/18 37/54 81/90 11/11*
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FB2 18/18* 25/54 49/90 6/10
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FB3 14/18 39/54 81/90 7/10
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FB4 9/18 25/54 81/90 10/10*
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FB5 4/18 7/54 4/90 3/10
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FB6 18/18* 23/54 26/90 10/10*
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FB7 18/18* 22/54 34/90 10/10*
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FB8 18/18* 36/54 55/90 10/10*
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----- ----- ----- -----
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106/144 214/432 411/720 67/81
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'CLK2X_IOB' mapped onto global clock net GCK1.
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Signal 'CLK_FSB' mapped onto global clock net GCK2.
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Signal 'CLK_IOB' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
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Signal 'nRES' mapped onto global set/reset net GSR.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 31 31 | I/O : 63 73
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Output : 32 32 | GCK/IO : 3 3
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Bidirectional : 0 0 | GTS/IO : 0 4
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GCK : 3 3 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 1 1 |
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---- ----
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Total 67 67
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** Power Data **
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There are 106 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'MXSE.ise'.
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************************* Summary of Mapped Logic ************************
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** 32 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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nDTACK_FSB 25 31 FB1_3 12 I/O O STD FAST RESET
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nADoutLE1 13 16 FB1_9 16 I/O O STD FAST SET
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nLDS_IOB 3 7 FB2_11 6 I/O O STD FAST RESET
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nUDS_IOB 3 7 FB2_12 7 I/O O STD FAST RESET
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RA<0> 2 3 FB2_14 8 I/O O STD FAST
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nDoutOE 2 7 FB2_15 9 I/O O STD FAST RESET
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nAS_IOB 1 5 FB2_17 10 I/O O STD FAST RESET
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nRAS 3 8 FB3_5 24 I/O O STD FAST
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nVMA_IOB 2 9 FB3_11 29 I/O O STD FAST RESET
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nRAMLWE 1 5 FB3_15 33 I/O O STD FAST
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RA<1> 2 3 FB4_2 87 I/O O STD FAST
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RA<5> 2 3 FB4_8 91 I/O O STD FAST
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nDinOE 2 6 FB4_12 94 I/O O STD FAST
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nRAMUWE 1 5 FB4_17 97 I/O O STD FAST
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nROMCS 2 5 FB5_2 35 I/O O STD FAST
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RA<3> 2 3 FB6_2 74 I/O O STD FAST
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RA<4> 2 3 FB6_6 77 I/O O STD FAST
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nCAS 1 1 FB6_9 79 I/O O STD FAST RESET
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nOE 1 2 FB6_12 81 I/O O STD FAST
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nROMWE 1 2 FB6_15 85 I/O O STD FAST
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nVPA_FSB 1 2 FB6_17 86 I/O O STD FAST
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RA<7> 2 3 FB7_2 50 I/O O STD FAST
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RA<8> 2 3 FB7_6 53 I/O O STD FAST
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RA<9> 2 3 FB7_9 55 I/O O STD FAST
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RA<11> 1 1 FB7_12 58 I/O O STD FAST
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nADoutLE0 1 2 FB7_15 60 I/O O STD FAST
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nDinLE 1 2 FB7_17 61 I/O O STD FAST RESET
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nBERR_FSB 4 9 FB8_2 63 I/O O STD FAST
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RA<2> 2 3 FB8_6 65 I/O O STD FAST
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RA<6> 2 3 FB8_9 67 I/O O STD FAST
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RA<10> 1 1 FB8_12 70 I/O O STD FAST
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nAoutOE 0 0 FB8_15 72 I/O O STD FAST
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** 74 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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fsb/BERR0r 3 8 FB1_10 STD RESET
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fsb/Ready2r 5 21 FB1_12 STD RESET
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$OpTx$INV$223 10 24 FB1_14 STD
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IORW0 14 18 FB1_16 STD RESET
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IOREQ 11 17 FB1_17 STD RESET
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iobm/IOS_FSM_FFd7 1 3 FB2_1 STD RESET
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iobm/IOS_FSM_FFd6 1 1 FB2_2 STD RESET
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iobm/IOS_FSM_FFd5 1 1 FB2_3 STD RESET
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iobm/IOS_FSM_FFd4 1 1 FB2_4 STD RESET
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iobm/IOS_FSM_FFd1 1 1 FB2_5 STD RESET
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iobm/BERRrr 1 1 FB2_6 STD RESET
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iobm/BERRrf 1 1 FB2_7 STD RESET
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iobm/IOS_FSM_FFd8 2 4 FB2_8 STD SET
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ALE0M 2 7 FB2_9 STD RESET
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iobm/IOS_FSM_FFd2 4 9 FB2_10 STD RESET
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iobm/IOS_FSM_FFd3 5 10 FB2_13 STD RESET
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IOBERR 8 11 FB2_16 STD RESET
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IOACT 10 15 FB2_18 STD RESET
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iobs/IORW1 15 17 FB3_3 STD RESET
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iobm/ETACK 1 6 FB3_4 STD RESET
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iobs/PS_FSM_FFd1 2 3 FB3_6 STD RESET
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iobs/IOReady 4 8 FB3_7 STD RESET
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BERR_IOBS 4 8 FB3_8 STD RESET
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ram/RS_FSM_FFd1 5 10 FB3_9 STD RESET
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ram/Once 5 10 FB3_10 STD RESET
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iobs/PS_FSM_FFd2 10 17 FB3_12 STD RESET
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iobs/Once 11 16 FB3_14 STD RESET
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fsb/Ready1r 5 15 FB3_16 STD RESET
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iobs/Load1 13 16 FB3_18 STD RESET
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ram/RS_FSM_FFd2 13 14 FB4_4 STD RESET
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ram/RASEL 20 15 FB4_6 STD RESET
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ram/RAMDIS1 18 15 FB4_10 STD RESET
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ram/RAMReady 16 15 FB4_14 STD RESET
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ram/RAMDIS2 7 15 FB4_18 STD RESET
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iobm/VPArr 1 1 FB5_16 STD RESET
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iobm/Er 1 1 FB5_17 STD RESET
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cnt/RefCnt<0> 0 0 FB5_18 STD RESET
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ram/BACTr 1 2 FB6_1 STD RESET
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iobs/IOACTr 1 1 FB6_3 STD RESET
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fsb/ASrf 1 1 FB6_4 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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cnt/RefCnt<3> 1 3 FB6_5 STD RESET
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cnt/RefCnt<2> 1 2 FB6_7 STD RESET
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cnt/RefCnt<1> 1 1 FB6_8 STD RESET
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RefAck 1 2 FB6_10 STD RESET
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ALE0S 1 2 FB6_11 STD RESET
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iobs/IOU1 2 2 FB6_13 STD RESET
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iobs/IOL1 2 2 FB6_14 STD RESET
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IOU0 3 5 FB6_16 STD RESET
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IOL0 3 5 FB6_18 STD RESET
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iobm/VPArf 1 1 FB7_1 STD RESET
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iobm/RESrr 1 1 FB7_3 STD RESET
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iobm/RESrf 1 1 FB7_4 STD RESET
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iobm/IOREQr 1 1 FB7_5 STD RESET
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iobm/Er2 1 1 FB7_7 STD RESET
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iobm/DTACKrr 1 1 FB7_8 STD RESET
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iobm/DTACKrf 1 1 FB7_10 STD RESET
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iobm/ES<3> 3 6 FB7_11 STD RESET
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iobm/ES<1> 3 4 FB7_13 STD RESET
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iobm/ES<0> 3 7 FB7_14 STD RESET
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iobm/ES<4> 4 7 FB7_16 STD RESET
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iobm/ES<2> 5 7 FB7_18 STD RESET
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fsb/VPA 14 12 FB8_1 STD RESET
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cnt/RefCnt<6> 1 6 FB8_3 STD RESET
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cnt/RefCnt<5> 1 5 FB8_4 STD RESET
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cnt/RefCnt<4> 1 4 FB8_5 STD RESET
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fsb/BERR1r 2 4 FB8_7 STD RESET
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cs/nOverlay1 2 3 FB8_8 STD RESET
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cs/nOverlay0 2 7 FB8_10 STD RESET
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cnt/RefDone 2 10 FB8_11 STD RESET
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fsb/Ready0r 3 8 FB8_13 STD RESET
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TimeoutB 3 12 FB8_14 STD RESET
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ram/RS_FSM_FFd3 11 14 FB8_16 STD RESET
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TimeoutA 3 11 FB8_17 STD RESET
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cnt/RefCnt<7> 1 7 FB8_18 STD RESET
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** 35 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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A_FSB<11> FB1_2 11 I/O I
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A_FSB<13> FB1_5 13 I/O I
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A_FSB<14> FB1_6 14 I/O I
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A_FSB<15> FB1_8 15 I/O I
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A_FSB<1> FB1_11 17 I/O I
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A_FSB<2> FB1_12 18 I/O I
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A_FSB<6> FB1_14 19 I/O I
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nUDS_FSB FB1_15 20 I/O I
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CLK2X_IOB FB1_17 22~ GCK/I/O GCK
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nRES FB2_2 99~ GSR/I/O GSR/I
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CLK_FSB FB3_2 23~ GCK/I/O GCK
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A_FSB<5> FB3_6 25 I/O I
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CLK_IOB FB3_8 27~ GCK/I/O GCK/I
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nVPA_IOB FB3_9 28 I/O I
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A_FSB<16> FB4_5 89 I/O I
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A_FSB<17> FB4_6 90 I/O I
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A_FSB<18> FB4_9 92 I/O I
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A_FSB<20> FB4_11 93 I/O I
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A_FSB<22> FB4_14 95 I/O I
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A_FSB<7> FB4_15 96 I/O I
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E_IOB FB5_15 46 I/O I
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nDTACK_IOB FB5_17 49 I/O I
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A_FSB<23> FB6_5 76 I/O I
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A_FSB<3> FB6_8 78 I/O I
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A_FSB<21> FB6_11 80 I/O I
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A_FSB<19> FB6_14 82 I/O I
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A_FSB<8> FB7_5 52 I/O I
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A_FSB<4> FB7_8 54 I/O I
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nBERR_IOB FB7_11 56 I/O I
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A_FSB<9> FB7_14 59 I/O I
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A_FSB<12> FB8_5 64 I/O I
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nWE_FSB FB8_8 66 I/O I
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A_FSB<10> FB8_11 68 I/O I
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nLDS_FSB FB8_14 71 I/O I
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nAS_FSB FB8_17 73 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
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*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 37/17
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Number of signals used by logic mapping into function block: 37
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 /\5 0 FB1_1 (b) (b)
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(unused) 0 0 \/5 0 FB1_2 11 I/O I
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nDTACK_FSB 25 20<- 0 0 FB1_3 12 I/O O
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(unused) 0 0 /\5 0 FB1_4 (b) (b)
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(unused) 0 0 /\5 0 FB1_5 13 I/O I
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(unused) 0 0 /\5 0 FB1_6 14 I/O I
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(unused) 0 0 0 5 FB1_7 (b)
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(unused) 0 0 \/5 0 FB1_8 15 I/O I
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nADoutLE1 13 8<- 0 0 FB1_9 16 I/O O
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fsb/BERR0r 3 1<- /\3 0 FB1_10 (b) (b)
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(unused) 0 0 /\1 4 FB1_11 17 I/O I
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fsb/Ready2r 5 0 0 0 FB1_12 18 I/O I
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(unused) 0 0 \/5 0 FB1_13 (b) (b)
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$OpTx$INV$223 10 5<- 0 0 FB1_14 19 I/O I
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(unused) 0 0 \/5 0 FB1_15 20 I/O I
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IORW0 14 9<- 0 0 FB1_16 (b) (b)
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IOREQ 11 10<- /\4 0 FB1_17 22 GCK/I/O GCK
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(unused) 0 0 /\5 0 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: A_FSB<10> 14: A_FSB<23> 26: fsb/Ready2r
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2: A_FSB<11> 15: A_FSB<9> 27: iobs/IOACTr
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3: A_FSB<12> 16: BERR_IOBS 28: iobs/IORW1
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4: A_FSB<13> 17: IORW0 29: iobs/IOReady
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5: A_FSB<14> 18: TimeoutA 30: iobs/Once
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6: A_FSB<15> 19: TimeoutB 31: iobs/PS_FSM_FFd1
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7: A_FSB<16> 20: cs/nOverlay1 32: iobs/PS_FSM_FFd2
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8: A_FSB<17> 21: fsb/ASrf 33: nADoutLE1
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9: A_FSB<18> 22: fsb/BERR0r 34: nAS_FSB
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10: A_FSB<19> 23: fsb/BERR1r 35: nDTACK_FSB
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11: A_FSB<20> 24: fsb/Ready0r 36: nWE_FSB
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12: A_FSB<21> 25: fsb/Ready1r 37: ram/RAMReady
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13: A_FSB<22>
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Signal 1 2 3 4 FB
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Name 0----+----0----+----0----+----0----+----0 Inputs
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nDTACK_FSB XXXXXXXXXXXXXXXX.XXXXXXXXX..X...XXXXX... 31
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nADoutLE1 ......XXXXXXXX.....XX........XXXXX.X.... 16
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fsb/BERR0r ..........XXXX....X.XX...........X...... 8
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fsb/Ready2r XXXXXXXXXXXXXXX..X.XX....X.......X.X.... 21
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$OpTx$INV$223 XXXXXXXXXXXXXXX..X.X...XXX..X...X..XX... 24
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IORW0 ......XXXXXXXX..X..XX......X.XXXXX.X.... 18
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IOREQ ......XXXXXXXX.....XX.....X..XXXXX.X.... 17
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 25/29
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Number of signals used by logic mapping into function block: 25
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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iobm/IOS_FSM_FFd7 1 1<- /\5 0 FB2_1 (b) (b)
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iobm/IOS_FSM_FFd6 1 0 /\1 3 FB2_2 99 GSR/I/O GSR/I
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iobm/IOS_FSM_FFd5 1 0 0 4 FB2_3 (b) (b)
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iobm/IOS_FSM_FFd4 1 0 0 4 FB2_4 (b) (b)
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iobm/IOS_FSM_FFd1 1 0 0 4 FB2_5 1 GTS/I/O (b)
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iobm/BERRrr 1 0 0 4 FB2_6 2 GTS/I/O (b)
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iobm/BERRrf 1 0 0 4 FB2_7 (b) (b)
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iobm/IOS_FSM_FFd8 2 0 0 3 FB2_8 3 GTS/I/O (b)
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ALE0M 2 0 0 3 FB2_9 4 GTS/I/O (b)
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iobm/IOS_FSM_FFd2 4 0 0 1 FB2_10 (b) (b)
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nLDS_IOB 3 0 0 2 FB2_11 6 I/O O
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nUDS_IOB 3 0 0 2 FB2_12 7 I/O O
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iobm/IOS_FSM_FFd3 5 0 0 0 FB2_13 (b) (b)
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RA<0> 2 0 0 3 FB2_14 8 I/O O
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nDoutOE 2 0 \/2 1 FB2_15 9 I/O O
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IOBERR 8 3<- 0 0 FB2_16 (b) (b)
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nAS_IOB 1 0 /\1 3 FB2_17 10 I/O O
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IOACT 10 5<- 0 0 FB2_18 (b) (b)
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Signals Used by Logic in Function Block
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1: A_FSB<10> 10: iobm/DTACKrf 18: iobm/IOS_FSM_FFd5
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2: A_FSB<1> 11: iobm/DTACKrr 19: iobm/IOS_FSM_FFd6
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3: CLK_IOB 12: iobm/ETACK 20: iobm/IOS_FSM_FFd7
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4: IOBERR 13: iobm/IOREQr 21: iobm/IOS_FSM_FFd8
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5: IOL0 14: iobm/IOS_FSM_FFd1 22: iobm/RESrf
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6: IORW0 15: iobm/IOS_FSM_FFd2 23: iobm/RESrr
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7: IOU0 16: iobm/IOS_FSM_FFd3 24: nBERR_IOB
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8: iobm/BERRrf 17: iobm/IOS_FSM_FFd4 25: ram/RASEL
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9: iobm/BERRrr
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Signal 1 2 3 4 FB
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Name 0----+----0----+----0----+----0----+----0 Inputs
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iobm/IOS_FSM_FFd7 ..X.........X.......X................... 3
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iobm/IOS_FSM_FFd6 ...................X.................... 1
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iobm/IOS_FSM_FFd5 ..................X..................... 1
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iobm/IOS_FSM_FFd4 .................X...................... 1
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iobm/IOS_FSM_FFd1 ..............X......................... 1
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iobm/BERRrr .......................X................ 1
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iobm/BERRrf .......................X................ 1
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iobm/IOS_FSM_FFd8 ..X.........XX......X................... 4
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ALE0M ............X..XXXXXX................... 7
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iobm/IOS_FSM_FFd2 ..X....XXXXX...X.....XX................. 9
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nLDS_IOB ....XX.........XXXXX.................... 7
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nUDS_IOB .....XX........XXXXX.................... 7
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iobm/IOS_FSM_FFd3 ..X....XXXXX...XX....XX................. 10
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RA<0> XX......................X............... 3
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nDoutOE .....X........XXXXXX.................... 7
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IOBERR ..XX...XXXXX...X.....XXX................ 11
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nAS_IOB ...............XXXXX.................... 5
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IOACT ..X....XXXXXX..XXXXXXXX................. 15
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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*********************************** FB3 ***********************************
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Number of function block inputs used/remaining: 39/15
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Number of signals used by logic mapping into function block: 39
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 /\3 2 FB3_1 (b) (b)
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(unused) 0 0 \/5 0 FB3_2 23 GCK/I/O GCK
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iobs/IORW1 15 10<- 0 0 FB3_3 (b) (b)
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iobm/ETACK 1 1<- /\5 0 FB3_4 (b) (b)
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nRAS 3 0 /\1 1 FB3_5 24 I/O O
|
||
iobs/PS_FSM_FFd1 2 0 0 3 FB3_6 25 I/O I
|
||
iobs/IOReady 4 0 \/1 0 FB3_7 (b) (b)
|
||
BERR_IOBS 4 1<- \/2 0 FB3_8 27 GCK/I/O GCK/I
|
||
ram/RS_FSM_FFd1 5 2<- \/2 0 FB3_9 28 I/O I
|
||
ram/Once 5 2<- \/2 0 FB3_10 (b) (b)
|
||
nVMA_IOB 2 2<- \/5 0 FB3_11 29 I/O O
|
||
iobs/PS_FSM_FFd2 10 5<- 0 0 FB3_12 30 I/O (b)
|
||
(unused) 0 0 \/5 0 FB3_13 (b) (b)
|
||
iobs/Once 11 6<- 0 0 FB3_14 32 I/O (b)
|
||
nRAMLWE 1 0 /\1 3 FB3_15 33 I/O O
|
||
fsb/Ready1r 5 0 0 0 FB3_16 (b) (b)
|
||
(unused) 0 0 \/5 0 FB3_17 34 I/O (b)
|
||
iobs/Load1 13 8<- 0 0 FB3_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<16> 14: fsb/ASrf 27: iobs/PS_FSM_FFd1
|
||
2: A_FSB<17> 15: fsb/Ready1r 28: iobs/PS_FSM_FFd2
|
||
3: A_FSB<18> 16: iobm/ES<0> 29: nADoutLE1
|
||
4: A_FSB<19> 17: iobm/ES<1> 30: nAS_FSB
|
||
5: A_FSB<20> 18: iobm/ES<2> 31: nLDS_FSB
|
||
6: A_FSB<21> 19: iobm/ES<3> 32: nVMA_IOB
|
||
7: A_FSB<22> 20: iobm/ES<4> 33: nWE_FSB
|
||
8: A_FSB<23> 21: iobm/VPArf 34: ram/Once
|
||
9: BERR_IOBS 22: iobm/VPArr 35: ram/RAMDIS1
|
||
10: IOACT 23: iobs/IOACTr 36: ram/RAMDIS2
|
||
11: IOBERR 24: iobs/IORW1 37: ram/RS_FSM_FFd1
|
||
12: RefAck 25: iobs/IOReady 38: ram/RS_FSM_FFd2
|
||
13: cs/nOverlay1 26: iobs/Once 39: ram/RS_FSM_FFd3
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
iobs/IORW1 XXXXXXXX....XX.........X.XXXXX..X....... 17
|
||
iobm/ETACK ...............XXXXX...........X........ 6
|
||
nRAS .....XXX...XX................X....XX.... 8
|
||
iobs/PS_FSM_FFd1 ......................X...XX............ 3
|
||
iobs/IOReady ..........X..X........X.XX.XXX.......... 8
|
||
BERR_IOBS ........X.X..X........X..X.XXX.......... 8
|
||
ram/RS_FSM_FFd1 .....XXX....XX...............X...X..XXX. 10
|
||
ram/Once .....XXX....XX...............X...X..XXX. 10
|
||
nVMA_IOB .........X.....XXXXXXX.........X........ 9
|
||
iobs/PS_FSM_FFd2 XXXXXXXX....XX........X..XXXXX..X....... 17
|
||
iobs/Once XXXXXXXX....XX...........XXXXX..X....... 16
|
||
nRAMLWE .............................XX.X.XX.... 5
|
||
fsb/Ready1r XXXXXXXX....XXX.........X...XX..X....... 15
|
||
iobs/Load1 XXXXXXXX....XX...........XXXXX..X....... 16
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB4 ***********************************
|
||
Number of function block inputs used/remaining: 25/29
|
||
Number of signals used by logic mapping into function block: 25
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
(unused) 0 0 \/2 3 FB4_1 (b) (b)
|
||
RA<1> 2 2<- \/5 0 FB4_2 87 I/O O
|
||
(unused) 0 0 \/5 0 FB4_3 (b) (b)
|
||
ram/RS_FSM_FFd2 13 10<- \/2 0 FB4_4 (b) (b)
|
||
(unused) 0 0 \/5 0 FB4_5 89 I/O I
|
||
ram/RASEL 20 15<- 0 0 FB4_6 90 I/O I
|
||
(unused) 0 0 /\5 0 FB4_7 (b) (b)
|
||
RA<5> 2 0 /\3 0 FB4_8 91 I/O O
|
||
(unused) 0 0 \/5 0 FB4_9 92 I/O I
|
||
ram/RAMDIS1 18 13<- 0 0 FB4_10 (b) (b)
|
||
(unused) 0 0 /\5 0 FB4_11 93 I/O I
|
||
nDinOE 2 0 /\3 0 FB4_12 94 I/O O
|
||
(unused) 0 0 \/5 0 FB4_13 (b) (b)
|
||
ram/RAMReady 16 11<- 0 0 FB4_14 95 I/O I
|
||
(unused) 0 0 /\5 0 FB4_15 96 I/O I
|
||
(unused) 0 0 /\1 4 FB4_16 (b) (b)
|
||
nRAMUWE 1 0 \/2 2 FB4_17 97 I/O O
|
||
ram/RAMDIS2 7 2<- 0 0 FB4_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<11> 10: cnt/RefCnt<6> 18: ram/BACTr
|
||
2: A_FSB<15> 11: cnt/RefCnt<7> 19: ram/Once
|
||
3: A_FSB<20> 12: cnt/RefDone 20: ram/RAMDIS1
|
||
4: A_FSB<21> 13: cs/nOverlay1 21: ram/RAMDIS2
|
||
5: A_FSB<22> 14: fsb/ASrf 22: ram/RASEL
|
||
6: A_FSB<23> 15: nAS_FSB 23: ram/RS_FSM_FFd1
|
||
7: A_FSB<2> 16: nUDS_FSB 24: ram/RS_FSM_FFd2
|
||
8: A_FSB<6> 17: nWE_FSB 25: ram/RS_FSM_FFd3
|
||
9: cnt/RefCnt<5>
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
RA<1> X.....X..............X.................. 3
|
||
ram/RS_FSM_FFd2 ...XXX..XXXXXXX..X....XXX............... 14
|
||
ram/RASEL ...XXX..XXXXXXX..XX...XXX............... 15
|
||
RA<5> .X.....X.............X.................. 3
|
||
ram/RAMDIS1 ...XXX..XXXXXXX..XX...XXX............... 15
|
||
nDinOE ..XXXX........X.X....................... 6
|
||
ram/RAMReady ...XXX..XXXXXXX..XX...XXX............... 15
|
||
nRAMUWE ..............XXX..XX................... 5
|
||
ram/RAMDIS2 ...XXX..XXXXXXX...X.X.XXX............... 15
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB5 ***********************************
|
||
Number of function block inputs used/remaining: 7/47
|
||
Number of signals used by logic mapping into function block: 7
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
(unused) 0 0 0 5 FB5_1 (b)
|
||
nROMCS 2 0 0 3 FB5_2 35 I/O O
|
||
(unused) 0 0 0 5 FB5_3 (b)
|
||
(unused) 0 0 0 5 FB5_4 (b)
|
||
(unused) 0 0 0 5 FB5_5 36 I/O
|
||
(unused) 0 0 0 5 FB5_6 37 I/O
|
||
(unused) 0 0 0 5 FB5_7 (b)
|
||
(unused) 0 0 0 5 FB5_8 39 I/O
|
||
(unused) 0 0 0 5 FB5_9 40 I/O
|
||
(unused) 0 0 0 5 FB5_10 (b)
|
||
(unused) 0 0 0 5 FB5_11 41 I/O
|
||
(unused) 0 0 0 5 FB5_12 42 I/O
|
||
(unused) 0 0 0 5 FB5_13 (b)
|
||
(unused) 0 0 0 5 FB5_14 43 I/O
|
||
(unused) 0 0 0 5 FB5_15 46 I/O I
|
||
iobm/VPArr 1 0 0 4 FB5_16 (b) (b)
|
||
iobm/Er 1 0 0 4 FB5_17 49 I/O I
|
||
cnt/RefCnt<0> 0 0 0 5 FB5_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<20> 4: A_FSB<23> 6: cs/nOverlay1
|
||
2: A_FSB<21> 5: E_IOB 7: nVPA_IOB
|
||
3: A_FSB<22>
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
nROMCS XXXX.X.................................. 5
|
||
iobm/VPArr ......X................................. 1
|
||
iobm/Er ....X................................... 1
|
||
cnt/RefCnt<0> ........................................ 0
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB6 ***********************************
|
||
Number of function block inputs used/remaining: 23/31
|
||
Number of signals used by logic mapping into function block: 23
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
ram/BACTr 1 0 0 4 FB6_1 (b) (b)
|
||
RA<3> 2 0 0 3 FB6_2 74 I/O O
|
||
iobs/IOACTr 1 0 0 4 FB6_3 (b) (b)
|
||
fsb/ASrf 1 0 0 4 FB6_4 (b) (b)
|
||
cnt/RefCnt<3> 1 0 0 4 FB6_5 76 I/O I
|
||
RA<4> 2 0 0 3 FB6_6 77 I/O O
|
||
cnt/RefCnt<2> 1 0 0 4 FB6_7 (b) (b)
|
||
cnt/RefCnt<1> 1 0 0 4 FB6_8 78 I/O I
|
||
nCAS 1 0 0 4 FB6_9 79 I/O O
|
||
RefAck 1 0 0 4 FB6_10 (b) (b)
|
||
ALE0S 1 0 0 4 FB6_11 80 I/O I
|
||
nOE 1 0 0 4 FB6_12 81 I/O O
|
||
iobs/IOU1 2 0 0 3 FB6_13 (b) (b)
|
||
iobs/IOL1 2 0 0 3 FB6_14 82 I/O I
|
||
nROMWE 1 0 0 4 FB6_15 85 I/O O
|
||
IOU0 3 0 0 2 FB6_16 (b) (b)
|
||
nVPA_FSB 1 0 0 4 FB6_17 86 I/O O
|
||
IOL0 3 0 0 2 FB6_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<13> 9: fsb/ASrf 17: nAS_FSB
|
||
2: A_FSB<14> 10: fsb/VPA 18: nLDS_FSB
|
||
3: A_FSB<4> 11: iobs/IOL1 19: nUDS_FSB
|
||
4: A_FSB<5> 12: iobs/IOU1 20: nWE_FSB
|
||
5: IOACT 13: iobs/Load1 21: ram/RASEL
|
||
6: cnt/RefCnt<0> 14: iobs/PS_FSM_FFd1 22: ram/RS_FSM_FFd1
|
||
7: cnt/RefCnt<1> 15: iobs/PS_FSM_FFd2 23: ram/RS_FSM_FFd2
|
||
8: cnt/RefCnt<2> 16: nADoutLE1
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
ram/BACTr ........X.......X....................... 2
|
||
RA<3> X.X.................X................... 3
|
||
iobs/IOACTr ....X................................... 1
|
||
fsb/ASrf ................X....................... 1
|
||
cnt/RefCnt<3> .....XXX................................ 3
|
||
RA<4> .X.X................X................... 3
|
||
cnt/RefCnt<2> .....XX................................. 2
|
||
cnt/RefCnt<1> .....X.................................. 1
|
||
nCAS ....................X................... 1
|
||
RefAck .....................XX................. 2
|
||
ALE0S .............XX......................... 2
|
||
nOE ................X..X.................... 2
|
||
iobs/IOU1 ............X.....X..................... 2
|
||
iobs/IOL1 ............X....X...................... 2
|
||
nROMWE ................X..X.................... 2
|
||
IOU0 ...........X.XXX..X..................... 5
|
||
nVPA_FSB .........X......X....................... 2
|
||
IOL0 ..........X..XXX.X...................... 5
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB7 ***********************************
|
||
Number of function block inputs used/remaining: 22/32
|
||
Number of signals used by logic mapping into function block: 22
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
iobm/VPArf 1 0 0 4 FB7_1 (b) (b)
|
||
RA<7> 2 0 0 3 FB7_2 50 I/O O
|
||
iobm/RESrr 1 0 0 4 FB7_3 (b) (b)
|
||
iobm/RESrf 1 0 0 4 FB7_4 (b) (b)
|
||
iobm/IOREQr 1 0 0 4 FB7_5 52 I/O I
|
||
RA<8> 2 0 0 3 FB7_6 53 I/O O
|
||
iobm/Er2 1 0 0 4 FB7_7 (b) (b)
|
||
iobm/DTACKrr 1 0 0 4 FB7_8 54 I/O I
|
||
RA<9> 2 0 0 3 FB7_9 55 I/O O
|
||
iobm/DTACKrf 1 0 0 4 FB7_10 (b) (b)
|
||
iobm/ES<3> 3 0 0 2 FB7_11 56 I/O I
|
||
RA<11> 1 0 0 4 FB7_12 58 I/O O
|
||
iobm/ES<1> 3 0 0 2 FB7_13 (b) (b)
|
||
iobm/ES<0> 3 0 0 2 FB7_14 59 I/O I
|
||
nADoutLE0 1 0 0 4 FB7_15 60 I/O O
|
||
iobm/ES<4> 4 0 0 1 FB7_16 (b) (b)
|
||
nDinLE 1 0 0 4 FB7_17 61 I/O O
|
||
iobm/ES<2> 5 0 0 0 FB7_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ALE0M 9: IOREQ 16: iobm/Er2
|
||
2: ALE0S 10: iobm/ES<0> 17: iobm/IOS_FSM_FFd3
|
||
3: A_FSB<17> 11: iobm/ES<1> 18: iobm/IOS_FSM_FFd4
|
||
4: A_FSB<18> 12: iobm/ES<2> 19: nDTACK_IOB
|
||
5: A_FSB<19> 13: iobm/ES<3> 20: nRES
|
||
6: A_FSB<20> 14: iobm/ES<4> 21: nVPA_IOB
|
||
7: A_FSB<8> 15: iobm/Er 22: ram/RASEL
|
||
8: A_FSB<9>
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
iobm/VPArf ....................X................... 1
|
||
RA<7> ..X...X..............X.................. 3
|
||
iobm/RESrr ...................X.................... 1
|
||
iobm/RESrf ...................X.................... 1
|
||
iobm/IOREQr ........X............................... 1
|
||
RA<8> ...X...X.............X.................. 3
|
||
iobm/Er2 ..............X......................... 1
|
||
iobm/DTACKrr ..................X..................... 1
|
||
RA<9> ....XX...............X.................. 3
|
||
iobm/DTACKrf ..................X..................... 1
|
||
iobm/ES<3> .........XXXX.XX........................ 6
|
||
RA<11> ....X................................... 1
|
||
iobm/ES<1> .........XX...XX........................ 4
|
||
iobm/ES<0> .........XXXXXXX........................ 7
|
||
nADoutLE0 XX...................................... 2
|
||
iobm/ES<4> .........XXXXXXX........................ 7
|
||
nDinLE ................XX...................... 2
|
||
iobm/ES<2> .........XXXXXXX........................ 7
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB8 ***********************************
|
||
Number of function block inputs used/remaining: 36/18
|
||
Number of signals used by logic mapping into function block: 36
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
fsb/VPA 14 9<- 0 0 FB8_1 (b) (b)
|
||
nBERR_FSB 4 4<- /\5 0 FB8_2 63 I/O O
|
||
cnt/RefCnt<6> 1 0 /\4 0 FB8_3 (b) (b)
|
||
cnt/RefCnt<5> 1 0 0 4 FB8_4 (b) (b)
|
||
cnt/RefCnt<4> 1 0 0 4 FB8_5 64 I/O I
|
||
RA<2> 2 0 0 3 FB8_6 65 I/O O
|
||
fsb/BERR1r 2 0 0 3 FB8_7 (b) (b)
|
||
cs/nOverlay1 2 0 0 3 FB8_8 66 I/O I
|
||
RA<6> 2 0 0 3 FB8_9 67 I/O O
|
||
cs/nOverlay0 2 0 0 3 FB8_10 (b) (b)
|
||
cnt/RefDone 2 0 0 3 FB8_11 68 I/O I
|
||
RA<10> 1 0 0 4 FB8_12 70 I/O O
|
||
fsb/Ready0r 3 0 0 2 FB8_13 (b) (b)
|
||
TimeoutB 3 0 0 2 FB8_14 71 I/O I
|
||
nAoutOE 0 0 \/4 1 FB8_15 72 I/O O
|
||
ram/RS_FSM_FFd3 11 6<- 0 0 FB8_16 (b) (b)
|
||
TimeoutA 3 0 /\2 0 FB8_17 73 I/O I
|
||
cnt/RefCnt<7> 1 0 \/4 0 FB8_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: $OpTx$INV$223 13: TimeoutB 25: fsb/ASrf
|
||
2: A_FSB<12> 14: cnt/RefCnt<0> 26: fsb/BERR0r
|
||
3: A_FSB<16> 15: cnt/RefCnt<1> 27: fsb/BERR1r
|
||
4: A_FSB<20> 16: cnt/RefCnt<2> 28: fsb/Ready0r
|
||
5: A_FSB<21> 17: cnt/RefCnt<3> 29: fsb/VPA
|
||
6: A_FSB<22> 18: cnt/RefCnt<4> 30: nAS_FSB
|
||
7: A_FSB<23> 19: cnt/RefCnt<5> 31: ram/Once
|
||
8: A_FSB<3> 20: cnt/RefCnt<6> 32: ram/RAMReady
|
||
9: A_FSB<7> 21: cnt/RefCnt<7> 33: ram/RASEL
|
||
10: BERR_IOBS 22: cnt/RefDone 34: ram/RS_FSM_FFd1
|
||
11: RefAck 23: cs/nOverlay0 35: ram/RS_FSM_FFd2
|
||
12: TimeoutA 24: cs/nOverlay1 36: ram/RS_FSM_FFd3
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
fsb/VPA X..XXXX..X..X...........XXX.XX.......... 12
|
||
nBERR_FSB ...XXXX..X..X............XX..X.......... 9
|
||
cnt/RefCnt<6> .............XXXXXX..................... 6
|
||
cnt/RefCnt<5> .............XXXXX...................... 5
|
||
cnt/RefCnt<4> .............XXXX....................... 4
|
||
RA<2> .X.....X........................X....... 3
|
||
fsb/BERR1r .........X..............X.X..X.......... 4
|
||
cs/nOverlay1 ......................X.X....X.......... 3
|
||
RA<6> ..X.....X.......................X....... 3
|
||
cs/nOverlay0 ...XXXX...............X.X....X.......... 7
|
||
cnt/RefDone ..........X..XXXXXXXXX.................. 10
|
||
RA<10> ....X................................... 1
|
||
fsb/Ready0r ....XXX................XX..X.X.X........ 8
|
||
TimeoutB ...........XXXXXXXXXX...X....X.......... 12
|
||
nAoutOE ........................................ 0
|
||
ram/RS_FSM_FFd3 ....XXX...........XXXX.XX....XX..XXX.... 14
|
||
TimeoutA ...........X.XXXXXXXX...X....X.......... 11
|
||
cnt/RefCnt<7> .............XXXXXXX.................... 7
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
******************************* Equations ********************************
|
||
|
||
********** Mapped Logic **********
|
||
|
||
|
||
$OpTx$INV$223 <= ((A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady AND NOT nADoutLE1)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||
A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||
NOT A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||
A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||
NOT A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
|
||
NOT iobs/IOReady)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||
NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady));
|
||
|
||
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
|
||
ALE0M_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOREQr)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd8));
|
||
|
||
FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,CLK_FSB,'0','0');
|
||
ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||
|
||
FTCPE_BERR_IOBS: FTCPE port map (BERR_IOBS,BERR_IOBS_T,CLK_FSB,'0','0');
|
||
BERR_IOBS_T <= ((iobs/Once AND NOT BERR_IOBS AND IOBERR AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1)
|
||
OR (BERR_IOBS AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (iobs/Once AND BERR_IOBS AND NOT IOBERR AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
|
||
OR (iobs/Once AND NOT BERR_IOBS AND IOBERR AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1));
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,CLK2X_IOB,'0','0');
|
||
IOACT_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
|
||
iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
|
||
iobm/RESrf AND iobm/RESrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
|
||
iobm/BERRrf AND iobm/BERRrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
|
||
iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
|
||
iobm/RESrf AND iobm/RESrr)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOREQr)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd8)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
|
||
NOT iobm/IOREQr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
|
||
NOT iobm/IOS_FSM_FFd8)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
|
||
iobm/BERRrf AND iobm/BERRrr));
|
||
|
||
FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,CLK2X_IOB,'0','0');
|
||
IOBERR_T <= ((NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/BERRrf AND iobm/BERRrr)
|
||
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/RESrf AND iobm/RESrr)
|
||
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/ETACK)
|
||
OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/ETACK)
|
||
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/BERRrf AND iobm/BERRrr)
|
||
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||
CLK_IOB AND iobm/RESrf AND iobm/RESrr));
|
||
|
||
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,CLK_FSB,'0','0',IOL0_CE);
|
||
IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
|
||
OR (iobs/IOL1 AND NOT nADoutLE1));
|
||
IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||
|
||
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,CLK_FSB,'0','0');
|
||
IOREQ_D <= ((EXP14_.EXP)
|
||
OR (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd1)
|
||
OR (NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1));
|
||
|
||
FTCPE_IORW0: FTCPE port map (IORW0,IORW0_T,CLK_FSB,'0','0');
|
||
IORW0_T <= ((A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT IORW0 AND nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT IORW0 AND nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND IORW0 AND
|
||
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND IORW0 AND
|
||
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND
|
||
nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (IORW0 AND NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (NOT IORW0 AND iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
|
||
|
||
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,CLK_FSB,'0','0',IOU0_CE);
|
||
IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
|
||
OR (iobs/IOU1 AND NOT nADoutLE1));
|
||
IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||
|
||
|
||
RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(1)));
|
||
|
||
|
||
RA(1) <= ((A_FSB(11) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(2)));
|
||
|
||
|
||
RA(2) <= ((A_FSB(12) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(3)));
|
||
|
||
|
||
RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(4)));
|
||
|
||
|
||
RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(5)));
|
||
|
||
|
||
RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(6)));
|
||
|
||
|
||
RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(7)));
|
||
|
||
|
||
RA(7) <= ((A_FSB(17) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(8)));
|
||
|
||
|
||
RA(8) <= ((A_FSB(9) AND ram/RASEL)
|
||
OR (A_FSB(18) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(9) <= ((A_FSB(20) AND ram/RASEL)
|
||
OR (A_FSB(19) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(10) <= A_FSB(21);
|
||
|
||
|
||
RA(11) <= A_FSB(19);
|
||
|
||
FDCPE_RefAck: FDCPE port map (RefAck,RefAck_D,CLK_FSB,'0','0');
|
||
RefAck_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
|
||
|
||
FTCPE_TimeoutA: FTCPE port map (TimeoutA,TimeoutA_T,CLK_FSB,'0','0');
|
||
TimeoutA_T <= ((TimeoutA AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT TimeoutA AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
|
||
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
|
||
OR (NOT TimeoutA AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
|
||
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
|
||
NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
|
||
|
||
FTCPE_TimeoutB: FTCPE port map (TimeoutB,TimeoutB_T,CLK_FSB,'0','0');
|
||
TimeoutB_T <= ((TimeoutB AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (TimeoutA AND NOT TimeoutB AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
|
||
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
|
||
OR (TimeoutA AND NOT TimeoutB AND NOT cnt/RefCnt(0) AND
|
||
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
|
||
|
||
FTCPE_cnt/RefCnt0: FTCPE port map (cnt/RefCnt(0),'1',CLK_FSB,'0','0');
|
||
|
||
FTCPE_cnt/RefCnt1: FTCPE port map (cnt/RefCnt(1),cnt/RefCnt(0),CLK_FSB,'0','0');
|
||
|
||
FTCPE_cnt/RefCnt2: FTCPE port map (cnt/RefCnt(2),cnt/RefCnt_T(2),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(2) <= (cnt/RefCnt(0) AND cnt/RefCnt(1));
|
||
|
||
FTCPE_cnt/RefCnt3: FTCPE port map (cnt/RefCnt(3),cnt/RefCnt_T(3),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(3) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2));
|
||
|
||
FTCPE_cnt/RefCnt4: FTCPE port map (cnt/RefCnt(4),cnt/RefCnt_T(4),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(4) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
|
||
cnt/RefCnt(3));
|
||
|
||
FTCPE_cnt/RefCnt5: FTCPE port map (cnt/RefCnt(5),cnt/RefCnt_T(5),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(5) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
|
||
cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||
|
||
FTCPE_cnt/RefCnt6: FTCPE port map (cnt/RefCnt(6),cnt/RefCnt_T(6),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(6) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(1) AND
|
||
cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||
|
||
FTCPE_cnt/RefCnt7: FTCPE port map (cnt/RefCnt(7),cnt/RefCnt_T(7),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(7) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||
cnt/RefCnt(1) AND cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||
|
||
FDCPE_cnt/RefDone: FDCPE port map (cnt/RefDone,cnt/RefDone_D,CLK_FSB,'0','0');
|
||
cnt/RefDone_D <= ((NOT cnt/RefDone AND NOT RefAck)
|
||
OR (NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND
|
||
NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND
|
||
NOT cnt/RefCnt(7)));
|
||
|
||
FTCPE_cs/nOverlay0: FTCPE port map (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,NOT nRES,'0');
|
||
cs/nOverlay0_T <= ((NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT cs/nOverlay0 AND NOT nAS_FSB)
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT cs/nOverlay0 AND fsb/ASrf));
|
||
|
||
FDCPE_cs/nOverlay1: FDCPE port map (cs/nOverlay1,cs/nOverlay0,CLK_FSB,'0','0',cs/nOverlay1_CE);
|
||
cs/nOverlay1_CE <= (nAS_FSB AND NOT fsb/ASrf);
|
||
|
||
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT CLK_FSB,'0','0');
|
||
|
||
FDCPE_fsb/BERR0r: FDCPE port map (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,'0','0');
|
||
fsb/BERR0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT TimeoutB AND NOT fsb/BERR0r)
|
||
OR (A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT fsb/BERR0r));
|
||
|
||
FDCPE_fsb/BERR1r: FDCPE port map (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,'0','0');
|
||
fsb/BERR1r_D <= ((NOT BERR_IOBS AND NOT fsb/BERR1r)
|
||
OR (nAS_FSB AND NOT fsb/ASrf));
|
||
|
||
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,'0','0');
|
||
fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||
NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady));
|
||
|
||
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,'0','0');
|
||
fsb/Ready1r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
|
||
NOT iobs/IOReady)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady AND NOT nADoutLE1));
|
||
|
||
FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
|
||
fsb/Ready2r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||
A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||
NOT A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||
A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||
NOT A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r));
|
||
|
||
FTCPE_fsb/VPA: FTCPE port map (fsb/VPA,fsb/VPA_T,CLK_FSB,'0','0');
|
||
fsb/VPA_T <= ((A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT fsb/BERR0r AND fsb/VPA AND NOT $OpTx$INV$223)
|
||
OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT BERR_IOBS AND NOT fsb/BERR1r AND NOT fsb/VPA AND NOT nAS_FSB AND NOT $OpTx$INV$223)
|
||
OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT BERR_IOBS AND NOT fsb/BERR1r AND NOT fsb/VPA AND fsb/ASrf AND NOT $OpTx$INV$223)
|
||
OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/VPA AND NOT nAS_FSB AND NOT $OpTx$INV$223)
|
||
OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/VPA AND fsb/ASrf AND NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(20) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(23) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(22) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(21) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (fsb/VPA AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT A_FSB(20) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(23) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(22) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223)
|
||
OR (NOT A_FSB(21) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||
NOT $OpTx$INV$223));
|
||
|
||
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,CLK2X_IOB,'0','0');
|
||
|
||
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),CLK2X_IOB,'0','0');
|
||
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
|
||
|
||
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),CLK2X_IOB,'0','0');
|
||
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
||
OR (NOT iobm/Er AND iobm/Er2));
|
||
|
||
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),CLK2X_IOB,'0','0');
|
||
iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
|
||
OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
|
||
OR (NOT iobm/Er AND iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
|
||
OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
|
||
|
||
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),CLK2X_IOB,'0','0');
|
||
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
|
||
|
||
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),CLK2X_IOB,'0','0');
|
||
iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||
iobm/ES(3) AND iobm/Er)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||
iobm/ES(3) AND NOT iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND iobm/ES(4)));
|
||
|
||
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,'0','0');
|
||
iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND iobm/ES(4));
|
||
|
||
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E_IOB,NOT CLK_IOB,'0','0');
|
||
|
||
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd2_D <= ((iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/ETACK)
|
||
OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/BERRrf AND
|
||
iobm/BERRrr)
|
||
OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/DTACKrf AND
|
||
iobm/DTACKrr)
|
||
OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/RESrf AND
|
||
iobm/RESrr));
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd3_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/ETACK)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/BERRrf AND
|
||
iobm/BERRrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/DTACKrf AND
|
||
iobm/DTACKrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/RESrf AND
|
||
iobm/RESrr));
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd7,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd7_D <= (NOT CLK_IOB AND iobm/IOREQr AND iobm/IOS_FSM_FFd8);
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd8: FDCPE port map (iobm/IOS_FSM_FFd8,iobm/IOS_FSM_FFd8_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd8_D <= ((NOT iobm/IOS_FSM_FFd8 AND NOT iobm/IOS_FSM_FFd1)
|
||
OR (NOT CLK_IOB AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1));
|
||
|
||
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,CLK_FSB,'0','0');
|
||
|
||
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,CLK_FSB,'0','0',iobs/Load1);
|
||
|
||
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,CLK_FSB,'0','0');
|
||
iobs/IORW1_T <= ((iobs/Once)
|
||
OR (NOT nADoutLE1)
|
||
OR (nWE_FSB AND iobs/IORW1)
|
||
OR (NOT nWE_FSB AND NOT iobs/IORW1)
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
|
||
OR (NOT A_FSB(19) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(18) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(17) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(16) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1)
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23))
|
||
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/IORW1));
|
||
|
||
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,CLK_FSB,'0','0');
|
||
iobs/IOReady_T <= ((iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (iobs/Once AND IOBERR AND iobs/IOReady AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
|
||
OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
|
||
OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1));
|
||
|
||
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,CLK_FSB,'0','0',iobs/Load1);
|
||
|
||
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,CLK_FSB,'0','0');
|
||
iobs/Load1_D <= ((iobs/Once)
|
||
OR (NOT nADoutLE1)
|
||
OR (NOT A_FSB(18) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(17) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1)
|
||
OR (NOT A_FSB(19) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(16) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB)
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23))
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
|
||
|
||
FTCPE_iobs/Once: FTCPE port map (iobs/Once,iobs/Once_T,CLK_FSB,'0','0');
|
||
iobs/Once_T <= ((A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||
NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||
NOT iobs/Once AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf)
|
||
OR (iobs/Once AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf));
|
||
|
||
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,'0','0');
|
||
iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
|
||
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
|
||
|
||
FTCPE_iobs/PS_FSM_FFd2: FTCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_T,CLK_FSB,'0','0');
|
||
iobs/PS_FSM_FFd2_T <= ((iobs/PS_FSM_FFd1 AND iobs/IOACTr)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||
NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||
NOT iobs/Once AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf));
|
||
|
||
|
||
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
||
|
||
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,CLK_FSB,'0','0');
|
||
nADoutLE1_D <= ((NOT A_FSB(19) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||
OR (NOT A_FSB(16) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
|
||
nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND nADoutLE1)
|
||
OR (NOT A_FSB(18) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||
OR (NOT A_FSB(17) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1 AND nADoutLE1)
|
||
OR (iobs/Once AND nADoutLE1)
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23) AND nADoutLE1)
|
||
OR (nAS_FSB AND NOT fsb/ASrf AND nADoutLE1)
|
||
OR (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
|
||
|
||
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB,nAS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||
nAS_IOB_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7);
|
||
|
||
|
||
nAoutOE <= '0';
|
||
|
||
|
||
nBERR_FSB <= ((nAS_FSB)
|
||
OR (NOT BERR_IOBS AND NOT fsb/BERR1r)
|
||
OR (NOT TimeoutB AND NOT fsb/BERR0r)
|
||
OR (A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT fsb/BERR0r));
|
||
|
||
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT CLK_FSB,'0','0');
|
||
|
||
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,'0','0');
|
||
nDTACK_FSB_D <= ((A_FSB(23) AND BERR_IOBS AND TimeoutB AND nDTACK_FSB)
|
||
OR (A_FSB(23) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||
OR (NOT A_FSB(22) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
|
||
OR (EXP17_.EXP)
|
||
OR (NOT A_FSB(20) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||
OR (NOT A_FSB(22) AND BERR_IOBS AND TimeoutB AND nDTACK_FSB)
|
||
OR (A_FSB(21) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
|
||
NOT iobs/IOReady AND nDTACK_FSB)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||
NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
|
||
OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB AND NOT nADoutLE1)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
||
NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND nDTACK_FSB)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND A_FSB(22) AND
|
||
A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||
NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND nDTACK_FSB)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||
A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND
|
||
nDTACK_FSB)
|
||
OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||
NOT A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND
|
||
nDTACK_FSB));
|
||
|
||
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
|
||
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
|
||
|
||
|
||
nDinOE <= ((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND nWE_FSB AND
|
||
NOT nAS_FSB));
|
||
|
||
FDCPE_nDoutOE: FDCPE port map (nDoutOE,nDoutOE_D,CLK2X_IOB,'0','0');
|
||
nDoutOE_D <= ((NOT IORW0)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd2));
|
||
|
||
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB,nLDS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||
nLDS_IOB_D <= ((NOT IOL0)
|
||
OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
|
||
|
||
|
||
nOE <= NOT ((nWE_FSB AND NOT nAS_FSB));
|
||
|
||
|
||
nRAMLWE <= NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||
NOT ram/RAMDIS1));
|
||
|
||
|
||
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||
NOT ram/RAMDIS1));
|
||
|
||
|
||
nRAS <= NOT (((RefAck)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||
NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)));
|
||
|
||
|
||
nROMCS <= NOT (((NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21))
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23) AND NOT A_FSB(21) AND
|
||
NOT cs/nOverlay1)));
|
||
|
||
|
||
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
|
||
|
||
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB,nUDS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||
nUDS_IOB_D <= ((NOT IOU0)
|
||
OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
|
||
|
||
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB,nVMA_IOB_T,CLK2X_IOB,'0','0');
|
||
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/ES(4))
|
||
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
|
||
|
||
|
||
nVPA_FSB <= NOT ((fsb/VPA AND NOT nAS_FSB));
|
||
|
||
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,CLK_FSB,'0','0');
|
||
ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
|
||
|
||
FTCPE_ram/Once: FTCPE port map (ram/Once,ram/Once_T,CLK_FSB,'0','0');
|
||
ram/Once_T <= ((NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
|
||
OR (ram/Once AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
|
||
|
||
FDCPE_ram/RAMDIS1: FDCPE port map (ram/RAMDIS1,ram/RAMDIS1_D,CLK_FSB,'0','0');
|
||
ram/RAMDIS1_D <= ((A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (nDinOE_OBUF.EXP)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||
OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||
OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd1 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND NOT fsb/ASrf)
|
||
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
|
||
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
|
||
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/BACTr AND fsb/ASrf));
|
||
|
||
FTCPE_ram/RAMDIS2: FTCPE port map (ram/RAMDIS2,ram/RAMDIS2_T,CLK_FSB,'0','0');
|
||
ram/RAMDIS2_T <= ((NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
|
||
OR (ram/RAMDIS2 AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||
ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||
OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
|
||
ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
|
||
cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
|
||
NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||
cnt/RefCnt(7))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
|
||
NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||
fsb/ASrf));
|
||
|
||
FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,CLK_FSB,'0','0');
|
||
ram/RAMReady_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (EXP36_.EXP)
|
||
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
|
||
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1)
|
||
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/BACTr AND fsb/ASrf)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1));
|
||
|
||
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,CLK_FSB,'0','0');
|
||
ram/RASEL_D <= ((ram/RS_FSM_FFd2.EXP)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (RA_5_OBUF.EXP)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||
NOT fsb/ASrf)
|
||
OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd1 AND
|
||
ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||
NOT fsb/ASrf)
|
||
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
|
||
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||
OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7)));
|
||
|
||
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,CLK_FSB,'0','0');
|
||
ram/RS_FSM_FFd1_T <= ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3));
|
||
|
||
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,CLK_FSB,'0','0');
|
||
ram/RS_FSM_FFd2_T <= ((RA_1_OBUF.EXP)
|
||
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
NOT cnt/RefCnt(5) AND ram/BACTr)
|
||
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/BACTr AND
|
||
NOT cnt/RefCnt(7))
|
||
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
NOT cnt/RefCnt(5) AND NOT fsb/ASrf)
|
||
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
NOT cnt/RefCnt(6) AND NOT fsb/ASrf)
|
||
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
NOT cnt/RefCnt(7) AND NOT fsb/ASrf)
|
||
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
|
||
OR (cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||
NOT cnt/RefCnt(6) AND ram/BACTr));
|
||
|
||
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,CLK_FSB,'0','0');
|
||
ram/RS_FSM_FFd3_T <= ((A_FSB(22) AND NOT A_FSB(21) AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||
OR (A_FSB(22) AND cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||
OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
|
||
OR (NOT cnt/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd2 AND
|
||
ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||
cnt/RefCnt(7))
|
||
OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
||
ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||
fsb/ASrf)
|
||
OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3)
|
||
OR (ram/Once AND cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
|
||
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(5))
|
||
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(6))
|
||
OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||
NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(7)));
|
||
|
||
Register Legend:
|
||
FDCPE (Q,D,C,CLR,PRE,CE);
|
||
FTCPE (Q,D,C,CLR,PRE,CE);
|
||
LDCP (Q,D,G,CLR,PRE);
|
||
|
||
****************************** Device Pin Out *****************************
|
||
|
||
Device : XC95144XL-10-TQ100
|
||
|
||
|
||
--------------------------------------------------
|
||
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
|
||
| 99 97 95 93 91 89 87 85 83 81 79 77 |
|
||
| 1 75 |
|
||
| 2 74 |
|
||
| 3 73 |
|
||
| 4 72 |
|
||
| 5 71 |
|
||
| 6 70 |
|
||
| 7 69 |
|
||
| 8 68 |
|
||
| 9 67 |
|
||
| 10 66 |
|
||
| 11 65 |
|
||
| 12 64 |
|
||
| 13 XC95144XL-10-TQ100 63 |
|
||
| 14 62 |
|
||
| 15 61 |
|
||
| 16 60 |
|
||
| 17 59 |
|
||
| 18 58 |
|
||
| 19 57 |
|
||
| 20 56 |
|
||
| 21 55 |
|
||
| 22 54 |
|
||
| 23 53 |
|
||
| 24 52 |
|
||
| 25 51 |
|
||
| 27 29 31 33 35 37 39 41 43 45 47 49 |
|
||
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
|
||
--------------------------------------------------
|
||
|
||
|
||
Pin Signal Pin Signal
|
||
No. Name No. Name
|
||
1 KPR 51 VCC
|
||
2 KPR 52 A_FSB<8>
|
||
3 KPR 53 RA<8>
|
||
4 KPR 54 A_FSB<4>
|
||
5 VCC 55 RA<9>
|
||
6 nLDS_IOB 56 nBERR_IOB
|
||
7 nUDS_IOB 57 VCC
|
||
8 RA<0> 58 RA<11>
|
||
9 nDoutOE 59 A_FSB<9>
|
||
10 nAS_IOB 60 nADoutLE0
|
||
11 A_FSB<11> 61 nDinLE
|
||
12 nDTACK_FSB 62 GND
|
||
13 A_FSB<13> 63 nBERR_FSB
|
||
14 A_FSB<14> 64 A_FSB<12>
|
||
15 A_FSB<15> 65 RA<2>
|
||
16 nADoutLE1 66 nWE_FSB
|
||
17 A_FSB<1> 67 RA<6>
|
||
18 A_FSB<2> 68 A_FSB<10>
|
||
19 A_FSB<6> 69 GND
|
||
20 nUDS_FSB 70 RA<10>
|
||
21 GND 71 nLDS_FSB
|
||
22 CLK2X_IOB 72 nAoutOE
|
||
23 CLK_FSB 73 nAS_FSB
|
||
24 nRAS 74 RA<3>
|
||
25 A_FSB<5> 75 GND
|
||
26 VCC 76 A_FSB<23>
|
||
27 CLK_IOB 77 RA<4>
|
||
28 nVPA_IOB 78 A_FSB<3>
|
||
29 nVMA_IOB 79 nCAS
|
||
30 KPR 80 A_FSB<21>
|
||
31 GND 81 nOE
|
||
32 KPR 82 A_FSB<19>
|
||
33 nRAMLWE 83 TDO
|
||
34 KPR 84 GND
|
||
35 nROMCS 85 nROMWE
|
||
36 KPR 86 nVPA_FSB
|
||
37 KPR 87 RA<1>
|
||
38 VCC 88 VCC
|
||
39 KPR 89 A_FSB<16>
|
||
40 KPR 90 A_FSB<17>
|
||
41 KPR 91 RA<5>
|
||
42 KPR 92 A_FSB<18>
|
||
43 KPR 93 A_FSB<20>
|
||
44 GND 94 nDinOE
|
||
45 TDI 95 A_FSB<22>
|
||
46 E_IOB 96 A_FSB<7>
|
||
47 TMS 97 nRAMUWE
|
||
48 TCK 98 VCC
|
||
49 nDTACK_IOB 99 nRES
|
||
50 RA<7> 100 GND
|
||
|
||
|
||
Legend : NC = Not Connected, unbonded pin
|
||
PGND = Unused I/O configured as additional Ground pin
|
||
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
||
KPR = Unused I/O with weak keeper (leave unconnected)
|
||
VCC = Dedicated Power Pin
|
||
GND = Dedicated Ground Pin
|
||
TDI = Test Data In, JTAG pin
|
||
TDO = Test Data Out, JTAG pin
|
||
TCK = Test Clock, JTAG pin
|
||
TMS = Test Mode Select, JTAG pin
|
||
PROHIBITED = User reserved pin
|
||
**************************** Compiler Options ****************************
|
||
|
||
Following is a list of all global compiler options used by the fitter run.
|
||
|
||
Device(s) Specified : xc95144xl-10-TQ100
|
||
Optimization Method : SPEED
|
||
Multi-Level Logic Optimization : ON
|
||
Ignore Timing Specifications : OFF
|
||
Default Register Power Up Value : LOW
|
||
Keep User Location Constraints : ON
|
||
What-You-See-Is-What-You-Get : OFF
|
||
Exhaustive Fitting : OFF
|
||
Keep Unused Inputs : OFF
|
||
Slew Rate : FAST
|
||
Power Mode : STD
|
||
Ground on Unused IOs : OFF
|
||
Set I/O Pin Termination : KEEPER
|
||
Global Clock Optimization : ON
|
||
Global Set/Reset Optimization : ON
|
||
Global Ouput Enable Optimization : ON
|
||
Input Limit : 54
|
||
Pterm Limit : 25
|
||
</pre>
|
||
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